Breakdown voltage detection circuit of NMOS transistor
By adding a diode to the breakdown voltage detection circuit of the NMOS transistor and utilizing its unidirectional conductivity, the generation of latch-up circuits and leakage paths is avoided, the problem of large leakage current is solved, and the normal mass production of PMIC products is ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2026-03-31
AI Technical Summary
The existing NMOS transistor breakdown voltage detection circuit has a large leakage current phenomenon, which makes it impossible for PMIC products to be mass-produced normally.
A diode is added between the input terminal and the first transistor. The unidirectional conductivity of the diode is used to reverse the circuit from the input terminal to the power supply VCC, preventing current from flowing through the first and second transistors to the gate of the third transistor, thereby avoiding the generation of latch-up circuit and the formation of leakage path.
The problem of large leakage current was solved, ensuring the normal mass production of PMIC products and improving the withstand voltage of the NMOS transistor breakdown voltage detection circuit to meet customer specifications.
Smart Images
Figure CN224066931U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a breakdown voltage detection circuit for an NMOS transistor. Background Technology
[0002] In the design of PMIC (Power Management Integrated Circuit) products, it is necessary to detect the breakdown voltage of one of the NMOS transistors. The current breakdown voltage detection circuit has a serious leakage phenomenon, which poses a serious risk of burnout, causing the entire wafer to be damaged and unusable, thus preventing the normal mass production of PMIC products. Utility Model Content
[0003] The purpose of this invention is to provide a breakdown voltage detection circuit for NMOS transistors, which can solve the problem of large leakage current and ensure normal mass production of the corresponding products.
[0004] To address the above problems, this invention provides a breakdown voltage detection circuit for an NMOS transistor, comprising a first transistor, a second transistor, a third transistor, and a diode. The first, second, and third transistors each include a gate terminal and two connection terminals. The first and second transistors are PMOS transistors, and the third transistor is an NMOS transistor.
[0005] One terminal of the first transistor and one terminal of the second transistor are both connected to the power supply VCC. The other terminal of the first transistor is connected to the positive terminal of the diode. One terminal of the third transistor is connected to the input terminal and connected to the input voltage, and is also connected to the negative terminal of the diode. The gate terminal of the first transistor is connected to both the other terminal of the second transistor and the gate terminal of the third transistor. The other terminal of the third transistor is grounded, and the gate terminal of the second transistor is connected to the gate voltage.
[0006] Optionally, one connection terminal of the first transistor is a drain region and the other connection terminal is a source region; or, one connection terminal of the first transistor is a source region and the other connection terminal is a drain region.
[0007] One connection terminal of the second transistor is the drain region, and the other connection terminal is the source region; or, one connection terminal of the second transistor is the source region, and the other connection terminal is the drain region.
[0008] Optionally, the third transistor is the object of detection in the breakdown voltage detection circuit;
[0009] One connection terminal of the third transistor is the drain region, and the other connection terminal is the source region.
[0010] Optionally, it also includes a fourth transistor and a fifth transistor, the negative terminal of the diode is also connected to one terminal of the fourth transistor, the gate terminal of the first transistor is also connected to one terminal of the fifth transistor, the gate terminal of the second transistor is also connected to the gate terminal of the fifth transistor, and the other terminals of the fourth transistor and the fifth transistor are both grounded.
[0011] Furthermore, both the fourth and fifth transistors are NMOS transistors, and one connection terminal of the fourth transistor and one connection terminal of the fifth transistor are both drain regions; the other connection terminal of the fourth transistor and the other connection terminal of the fifth transistor are both source regions.
[0012] Optionally, the structure of the diode and the first transistor includes a P-type substrate, a first well region, a second well region, a first doped region, a second doped region, a third doped region, a body region, and a gate structure.
[0013] The first well region is located in the P-type substrate, and the gate structure is located on the P-type substrate of the first well region. The second well region, the first doped region, and the body region are all disposed in the first well region. The first doped region and the body region are disposed adjacent to each other on one side of the gate structure. The first doped region is located between the first doped region body region and the gate structure. The second well region is disposed on the other side of the gate structure. The second doped region and the third doped region are disposed adjacent to each other in the second well region. The second doped region is located between the gate structure and the third doped region.
[0014] Furthermore, the first well region is an N-type well region, and the second well region is a P-type well region.
[0015] Furthermore, both the first and second doped regions are doped with P-type ions, and both the third doped region and the bulk region are doped with N-type ions.
[0016] Furthermore, the second doped region and the third doped region constitute the diode, and the first doped region, the gate structure, and the second doped region constitute the first transistor.
[0017] Furthermore, the first doped region is connected to the power supply VCC, and the third doped region is connected to the input terminal.
[0018] Compared with the prior art, the present invention has the following beneficial effects:
[0019] This invention provides a breakdown voltage detection circuit for an NMOS transistor, comprising a first transistor, a second transistor, a third transistor, and a diode. Each of the first, second, and third transistors includes a gate terminal and two connection terminals. The first and second transistors are PMOS transistors, and the third transistor is an NMOS transistor. One connection terminal of the first transistor and one connection terminal of the second transistor are both connected to the power supply VCC. The other connection terminal of the first transistor is connected to the anode of the diode. One connection terminal of the third transistor is connected to the input terminal and receives the input voltage, and is also connected to the cathode of the diode. The gate terminal of the first transistor is simultaneously connected to the other connection terminal of the second transistor and the gate terminal of the third transistor. The other connection terminal of the third transistor is grounded, and the gate terminal of the second transistor receives the gate voltage. This invention adds a diode between the input terminal and the first transistor. Utilizing the unidirectional conductivity of the diode, the current flows from the input terminal to the power supply VCC in reverse, effectively cutting off the circuit. When the input voltage increases and exceeds the voltage provided by the power supply VCC, no current flows from the input terminal through the first and second transistors to the gate of the third transistor. This prevents the third transistor from turning on, avoiding the generation of latch-up circuits and leakage paths, thus solving the problem of large leakage and ensuring the normal mass production of PMIC products. Attached Figure Description
[0020] Figure 1 This is a circuit diagram of a breakdown voltage detection circuit for an NMOS transistor.
[0021] Figures 2-3 This is a schematic diagram of transistor Q3 when a large leakage current occurs during the breakdown voltage detection process.
[0022] Figure 4 for Figure 1 A schematic diagram of the structure of the third transistor.
[0023] Figure 5 This is a circuit diagram of a breakdown voltage detection circuit for an NMOS transistor provided in one embodiment of the present invention.
[0024] Figure 6 This is a schematic diagram of the integrated structure of a first transistor and a diode provided in an embodiment of the present invention.
[0025] Explanation of reference numerals in the attached figures:
[0026] 10 - P-type substrate; 11 - First well region; 12 - First doped region; 13 - Body region; 14 - Second well region; 15 - Second doped region; 16 - Third doped region; 20 - Gate structure. Detailed Implementation
[0027] The following is a further detailed description of a breakdown voltage detection circuit for an NMOS transistor according to the present invention. The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.
[0028] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would confuse the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0029] To make the objectives and features of this utility model clearer and easier to understand, the specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model.
[0030] like Figure 1 As shown, in a current PMIC (Power Management Integrated Circuit) product, the breakdown voltage detection circuit for an NMOS transistor uses PMOS transistors Q1 and Q2, while Q3, Q4, and Q5 are all NMOS transistors. Transistor Q3 is the transistor being detected by the breakdown voltage detection circuit. Figure 1 In the circuit, when the input voltage Vin is greater than the source voltage VCC, transistors Q1 and Q2 turn on, and current flows from the input terminal through transistor Q1, then through transistor Q2, and finally into the gate of transistor Q3, causing transistor Q3 to turn on. When transistor Q3 turns on, a latch-up loop is generated in transistor Q3 between the input voltage Vin and ground GND. Thus, the input voltage Vin will directly leak to ground GND through the latch-up loop, making transistor Q3 a leakage path. This results in a large leakage current between the input voltage Vin and ground GND, that is, the leakage current increases from the specified 20mA to the actual leakage current greater than 100mA.
[0031] like Figures 2-3As shown, the principle of latch-up circuit generation is as follows: In the NMOS transistor between the input voltage Vin and ground GND, a low-impedance path is generated due to the interaction of the parasitic vertical PNP and lateral NPN bipolar BJT. The lateral NPN can gradually increase the conduction degree of the vertical PNP. The greater the conduction of the vertical PNP, the greater the current fed back to the lateral NPN (i.e., the greater the conduction of the lateral NPN). Finally, the lateral NPN and the vertical PNP are in a state of extremely low resistance conduction. At this time, the input voltage Vin and ground GND are approximately short-circuited, resulting in a large leakage current between the input terminal and ground GND.
[0032] like Figure 4 As shown, during the breakdown voltage detection process, the P+ lead-out region 1 and the N-well region Nwell at the input terminal connection of transistor Q3 are at the same potential, and the voltage is equal to the input voltage Vin (e.g., 5V), which is greater than the source voltage VCC. At this time, transistor Q3 is turned on, and vertically, the P+ lead-out region 1, the N-well region Nwell, and the P-type substrate Psub of transistor Q3 form a PNP structure Q. PNP Laterally, the N-well region (Nwell), P-well region (Pwell), and N+ doped region 2 at the ground connection point of transistor Q3 constitute the NPN structure Q. NPN .
[0033] When transistor Q3 is turned on, a conductive channel is first formed in transistor Q3. This conductive channel shares the voltage of the N-well region, causing a drop in the N-well voltage at the input voltage Vin connection point. Then, a voltage drop exists between the P+ lead-out region 1 and the N-well region. Next, vertically, the PNP structure Q... PNP When the circuit is turned on, the input voltage Vin leaks directly to the P-type substrate Psub (i.e., ground GND); subsequently, the current on the P-type substrate Psub causes the lateral NPN structure Q to... NPN Conduction, finally the PNP structure Q PNP With NPN structure Q NPN This creates a latch-up loop, resulting in a large leakage current (e.g., leakage current exceeding 100mA) between the input terminal and ground (GND).
[0034] like Figure 5 As shown, this embodiment provides a breakdown voltage detection circuit for an NMOS transistor, including a first transistor Q1, a second transistor Q2, a third transistor Q3, and a diode. The first transistor Q1, the second transistor Q2, and the third transistor Q3 each include a gate terminal and two connection terminals. The first transistor Q1 and the second transistor Q2 are PMOS transistors, and the third transistor Q3 is an NMOS transistor.
[0035] One terminal of the first transistor Q1 and one terminal of the second transistor Q2 are both connected to the power supply VCC. The other terminal of the first transistor Q1 is connected to the positive terminal of the diode. One terminal of the third transistor Q3 is connected to the input terminal and connected to the input voltage Vin, and is also connected to the negative terminal of the diode. The gate terminal of the first transistor Q1 is connected to both the other terminal of the second transistor Q2 and the gate terminal of the third transistor Q3. The other terminal of the third transistor Q3 is grounded. The gate terminal of the second transistor Q2 is connected to the gate voltage Vg.
[0036] This embodiment adds a diode between the input terminal and the first transistor Q1. Utilizing the unidirectional conductivity of the diode, the current flows from the input terminal to the power supply VCC in reverse, effectively cutting off the circuit. When the input voltage increases and exceeds the voltage provided by the power supply VCC, no current flows from the input terminal through the first transistor Q1 and the second transistor Q2 to the gate of the third transistor Q3. As a result, the third transistor Q3 will not turn on, avoiding the generation of latch-up circuits and leakage paths, thus solving the problem of large leakage and ensuring the normal mass production of PMIC products.
[0037] In detail, the breakdown voltage detection circuit includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5. The first transistor Q1 and the second transistor Q2 are both PMOS transistors, and the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are all NMOS transistors.
[0038] One terminal of the first transistor Q1 and one terminal of the second transistor Q2 are simultaneously connected to the power supply VCC. The other terminal of the first transistor Q1 is connected to the positive terminal of the diode. The negative terminal of the diode is simultaneously connected to one terminal of the third transistor Q3, one terminal of the fourth transistor Q4, and the input terminal. The gate terminal of the first transistor Q1 is simultaneously connected to the other terminal of the second transistor Q2, the gate terminal of the third transistor Q3, and one terminal of the fifth transistor Q5. The gate terminal of the second transistor Q2 is connected to a gate voltage source and is also connected to the gate terminal of the fifth transistor Q5. The other terminal of the fourth transistor Q4, the other terminal of the third transistor Q3, the substrate of the third transistor Q3, and the other terminal of the fifth transistor Q5 are all grounded.
[0039] The third transistor Q3 is the NOMS transistor being detected by the breakdown voltage detection circuit. One connection terminal of the first transistor Q1 can be the drain region and the other connection terminal can be the source region; or, one connection terminal of the first transistor Q1 can be the source region and the other connection terminal can be the drain region. One connection terminal of the second transistor Q2 can be the drain region and the other connection terminal can be the source region; or, one connection terminal of the second transistor Q2 can be the source region and the other connection terminal can be the drain region.
[0040] One connection terminal of the third transistor Q3, one connection terminal of the fourth transistor Q4, and one connection terminal of the fifth transistor Q5 are all drain regions; the other connection terminal of the third transistor Q3, the other connection terminal of the fourth transistor Q4, and the other connection terminal of the fifth transistor Q5 are all source regions.
[0041] like Figure 6 As shown, in the semiconductor structure, the diode is integrated into the structure of the first transistor Q1. Specifically, the structure of the diode and the first transistor Q1 includes a P-type substrate 10, a first well region 11, a second well region 14, a first doped region 12, a second doped region 15, a third doped region 16, a body region 13, and a gate structure 20.
[0042] The first well region 11 is located in the P-type substrate 10, and the gate structure 20 is located on the P-type substrate 10 of the first well region 11. The second well region 14, the first doped region 12, and the body region 13 are all disposed in the first well region 11. The first doped region 12 and the body region 13 are disposed adjacent to each other on one side of the gate structure 20, and the first doped region 12 is located between the body region 13 and the gate structure 20. The second well region 14 is disposed on the other side of the gate structure 20. The second doped region 15 and the third doped region 16 are disposed adjacent to each other in the second well region 14, and the second doped region 15 is located between the gate structure 20 and the third doped region 16.
[0043] In this embodiment, the first well region 11 is an N-type well region, the second well region 14 is a P-type well region, the first doped region 12 and the second doped region 15 are both doped with P-type ions, and the third doped region 16 and the body region 13 are both doped with N-type ions. The second doped region 15 and the third doped region 16 constitute a diode, and the first doped region 12, the gate structure 20, and the second doped region 15 constitute a first transistor Q1. The first doped region 12 is connected to the power supply VCC, and the third doped region 16 is connected to the input terminal. This embodiment uses the second doped region 15, the third doped region 16, and the second well region 14 instead of the existing technology that only forms the second doped region 15. The diode can be added through a simple process, and the existing large leakage problem can be solved without adding a complicated process.
[0044] In this embodiment, a diode is added between the input terminal and the power supply VCC. Utilizing the unidirectional conduction characteristic of the diode, the input terminal and the power supply VCC are reverse-biased and cut off. Thus, when the input voltage increases and exceeds the voltage provided by the power supply VCC, no current flows through the diode into the first transistor Q1. Consequently, no current flows through the first transistor Q1 and the second transistor Q2 to the gate of the third transistor Q3. Therefore, the third transistor Q3 will not be turned on, and no channel will be generated. The voltage of the first doped region 12 will not decrease due to the voltage division of the channel. As a result, the vertical PN junction in the third transistor Q3 will not conduct, and no PNP conduction loop is formed. This avoids the generation of latch-up loops and leakage paths, solves the problem of large leakage, and ensures the normal mass production of the corresponding products.
[0045] This invention provides a breakdown voltage detection circuit for an NMOS transistor, comprising a first transistor, a second transistor, a third transistor, and a diode. Each of the first, second, and third transistors includes a gate terminal and two connection terminals. The first and second transistors are PMOS transistors, and the third transistor is an NMOS transistor. One connection terminal of the first transistor and one connection terminal of the second transistor are both connected to the power supply VCC. The other connection terminal of the first transistor is connected to the anode of the diode. One connection terminal of the third transistor is connected to the input terminal and receives the input voltage, and is also connected to the cathode of the diode. The gate terminal of the first transistor is connected to both the other connection terminal of the second transistor and the gate terminal of the third transistor. The other connection terminal of the third transistor is grounded. The gate terminal of the second transistor receives the gate voltage. This invention improves the withstand voltage of the NMOS transistor breakdown voltage detection circuit in PMIC products, solves the problem of large leakage current, ensures product application and meets customer specifications, thus guaranteeing normal mass production of the corresponding products.
[0046] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0047] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A breakdown voltage detection circuit of an NMOS transistor, characterized by, The circuit comprises a first transistor, a second transistor, a third transistor and a diode, the first transistor, the second transistor and the third transistor each comprise a gate terminal and two connection terminals, the first transistor and the second transistor are PMOS transistors, and the third transistor is an NMOS transistor, one connection terminal of the first transistor and one connection terminal of the second transistor are connected to a power supply VCC, the other connection terminal of the first transistor is connected to the positive electrode of the diode, one connection terminal of the third transistor is connected to an input terminal and inputs an input voltage, and is connected to the negative electrode of the diode, the gate terminal of the first transistor is connected to the other connection terminal of the second transistor and the gate terminal of the third transistor, the other connection terminal of the third transistor is connected to ground, and the gate terminal of the second transistor inputs a gate voltage.
2. The circuit of claim 1, wherein one connection terminal of the first transistor is a drain region, and the other connection terminal of the first transistor is a source region; or one connection terminal of the first transistor is a source region, and the other connection terminal of the first transistor is a drain region. one connection terminal of the second transistor is a drain region, and the other connection terminal of the second transistor is a source region; or one connection terminal of the second transistor is a source region, and the other connection terminal of the second transistor is a drain region.
3. The circuit of claim 1, wherein the third transistor is a detection object of the circuit. one connection terminal of the third transistor is a drain region, and the other connection terminal of the third transistor is a source region.
4. The NMOS transistor breakdown voltage detection circuit of claim 1, wherein, The circuit further comprises a fourth transistor and a fifth transistor, the negative electrode of the diode is further connected to one connection terminal of the fourth transistor, the gate terminal of the first transistor is further connected to one connection terminal of the fifth transistor, the gate terminal of the second transistor is further connected to the gate terminal of the fifth transistor, and the other connection terminal of the fourth transistor and the other connection terminal of the fifth transistor are both connected to ground.
5. The breakdown voltage detection circuit of the NMOS transistor according to claim 4, wherein The fourth transistor and the fifth transistor are both NMOS transistors, one connection terminal of the fourth transistor and one connection terminal of the fifth transistor are both drain regions, and the other connection terminal of the fourth transistor and the other connection terminal of the fifth transistor are both source regions.
6. The breakdown voltage detection circuit of an NMOS transistor according to claim 1, wherein, The structure of the diode and the first transistor comprises a P-type substrate, a first well region, a second well region, a first doped region, a second doped region, a third doped region, a body region and a gate structure, the first well region is located in the P-type substrate, the gate structure is located on the P-type substrate of the first well region, the second well region, the first doped region and the body region are all arranged in the first well region, the first doped region and the body region are arranged adjacent to each other on one side of the gate structure, the first doped region is located between the first doped region, the body region and the gate structure, the second well region is arranged on the other side of the gate structure, and the second doped region and the third doped region are arranged adjacent to each other in the second well region, and the second doped region is located between the gate structure and the third doped region.
7. The NMOS transistor breakdown voltage detection circuit of claim 6, wherein, The first well region is an N-type well region, and the second well region is a P-type well region.
8. The NMOS transistor breakdown voltage detection circuit of claim 6, wherein, The first and second doped regions are doped with P-type ions, and the third doped region and the body region are doped with N-type ions.
9. The NMOS transistor breakdown voltage detection circuit of claim 6, wherein, The second and third doped regions form the diode, and the first doped region, the gate structure and the second doped region form the first transistor.
10. The breakdown voltage detection circuit of the NMOS transistor according to claim 6, wherein, The first doped region is connected to a power supply VCC, and the third doped region is connected to the input terminal.