Data processing system and method for predictively selecting a scope of a prefetch operation

Abstract

A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, anda cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.

Description

technical field [0001] The present invention relates generally to data processing, and more particularly to data processing in a data processing system having multiple broadcast communication ranges. Background technique [0002] A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically includes one or more address, data, and control buses. Coupled to the system interconnect is system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and is generally read and write accessible by all processing units. To reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, wherein the lower levels of the cache hierarchy may be accessed by a or more processor cores to share. [0003] Because multip...

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