Processor and its frequency-reducing device and method

Abstract

The invention discloses a processor and the frequency reducing device and method. And the frequency reducing device comprises a multi-bit state converter, a multichannel selector, a frequency reduction coefficient register, and a gated clock circuit, where the frequency reducing device receives original clock and real-timely reads value of the frequency reduction coefficient register, and gates the original clock, so as to complete a function of reducing frequency of original clock. And it can implement a function of dynamically reducing frequency of processor kernel by simple digital logic circuit and at very low cost and the frequency reduction has features of small spacing granularity and high real-timeness, thus completely applying to various universal processors, embedded processors and SOC to achieve the purpose of reducing average operating power consumption of processors and saving electric energy.

Description

technical field [0001] The present invention relates to the technical field of processors, in particular to the technical field of processors and their low power consumption. frequency technology. Background technique [0002] In the design of processor chips, power consumption has become another important technical indicator besides processor performance. Whether in the field of general-purpose processors or in the field of embedded processors, low-power processor design has Wide range of needs and application spaces. [0003] Since the power consumption of the processor is directly proportional to the clock frequency of the processor, dynamically changing the frequency of the processor according to the needs of the running program during the running of the processor has become an effective means to reduce the power consumption of the processor. [0004] In the prior art, the processor receives a low-frequency external clock, and then multiplies the frequency of the clock...

AI Technical Summary

Problems solved by technology

[0009] But its disadvantage is that it can only output clocks divided by even multiples of the original clock frequency, that is, the clock frequency after frequency reduction can only be 1 / 2, 1 / 4, 1 / 6, 1 / 8, etc. of the original clock frequency. Therefore, the interval granularity of frequency reduction is too large, which affects the effect of frequency reduction

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