Dynamic frequency conversion device for core of processor under SOC architecture and method

Abstract

The present invention discloses a processor kernel dynamic frequency conversion device under SOC structure and its method. Said frequency conversion device includes processor kernel and main phase-locked loop and auxiliary phase-locked loop which can be used for providing chock signal for processor kernel, the varial frequency register for storing frequency conversion coefficient is connected with main phase-locked loop, and the clock switching circuit can be used for switching clock signals outputted by main phase-locked loop and auxiliary phase-locked loop, and can provide one of clock signals outputted by main phase-locked loop and auxiliary phase-locked loop for processor kernel. Said clock switching circuit includes a frequency conversion mark input end, and said input end can receive frequency conversion mark signal.

Description

technical field [0001] The present invention relates to the field of CPU / SOC, more specifically, the present invention relates to the processor core dynamic frequency conversion technology under the SOC framework. Background technique [0002] In the field of embedded applications, people have placed power consumption and cost in a more important position, and the market has put forward a strong demand for the controllability of the main frequency of the processor, especially in occasions where power consumption needs to be strictly controlled. [0003] In the prior art, the main frequency of the processor is provided with a clock signal by a phase-locked loop (PLL). There are usually two methods for traditional processor frequency conversion. The first method is to configure the phase-locked loop PLL frequency selection through the code stream (two serial bits) during the initialization stage of the chip group, such as the R4000 series; the other method It is to add pins o...

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