Device for supporting dynamic frequency conversion of IP module

A dynamic frequency and frequency converter technology, applied in electrical components, pulse technology, etc., can solve the problems of changing frequency, prolonging the dynamic frequency conversion time of the processor, reducing power consumption, etc., to shorten the time, reduce power consumption, and realize dynamic frequency conversion. Effect

Active Publication Date: 2014-12-24
C SKY MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the current frequency conversion device, the frequency conversion is usually static, that is, the effect of frequency conversion can only be achieved by changing the ratio of the system clock to the processor clock when the system is started, so that the program cannot be dynamically changed according to its own needs. frequency, reducing the possibility of power reduction
In some current dynamic frequency conversion devices, it is usually necessary to execute some special instructions such as low-power instructions to make the processor enter a special state and then dynamically change the processor frequency. This method will prolong the time for dynamic frequency conversion of the processor.

Method used

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  • Device for supporting dynamic frequency conversion of IP module
  • Device for supporting dynamic frequency conversion of IP module
  • Device for supporting dynamic frequency conversion of IP module

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Embodiment Construction

[0021] The present invention will be further described below in conjunction with the accompanying drawings.

[0022] refer to Figure 1 to Figure 6 , a device supporting dynamic frequency conversion of an IP module, comprising a clock frequency divider for receiving a reference clock and generating multiple groups of clock signals and clock enable signals with different frequency division ratios; a clock frequency converter for The current processor clock signal, the processor clock enable signal and the system clock signal are generated according to the current frequency division ratio signal; a processor bus interface is used for communication between the processor and the bus. in:

[0023] The clock frequency divider receives a reference clock as its input, and its output terminal is connected to the input terminal of the clock frequency converter.

[0024] The clock frequency converter receives the clock frequency division ratio signal as one of its inputs, and receives ...

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Abstract

The invention relates to a device for supporting dynamic frequency conversion of an IP module. The device comprises a clock frequency divider and an IP module bus interface, wherein the clock frequency divider is used for receiving a reference clock and generating a plurality of groups of clock signals and clock enabling signals with different clock frequency division ratios; the IP module bus interface is used for communication of the IP module and a bus, and is in communication connection with the bus; the clock frequency divider is used for generating a current IP clock enabling signal, a IP clock enabling signal and a system lock signal according to a current frequency division ratio signal; and the output end of the clock frequency divider is connected with the input end of the clock frequency divider, and the output end of the clock frequency divider is connected with a bus interface and the bus of the IP module. According to the invention, power consumption can be reduced, and frequency change time is shortened.

Description

technical field [0001] The invention relates to the field of SOC / CPU, more specifically, the invention relates to a device supporting dynamic frequency conversion of IP modules. Background technique [0002] In integrated circuit design, power consumption is increasingly becoming a top concern, affecting design feasibility, cost, and reliability. [0003] Since the power consumption is directly proportional to the frequency, the purpose of reducing power consumption can be achieved by reducing the frequency. [0004] In the current SOC architecture, some IP blocks (such as processor blocks) work at a certain clock frequency, while buses and other IP blocks work at another clock frequency. Most of the programs do not require the processor module to always work at the highest frequency. When the processor does not need to work at full capacity, its frequency can be reduced, which can not only meet the needs of the program, but also reduce power consumption. Normally the syst...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K21/10
Inventor 葛海通王荣华杨军孟建熠
Owner C SKY MICROSYST CO LTD
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