Dynamic frequency conversion device of bus in high speed and kermel interface of processor under SOC architecture

A processor core and processor technology, applied in the direction of electrical digital data processing, instrumentation, signal generation/distribution, etc., can solve the problems of restarting the system, lack of flexibility, etc., and achieve the effect of saving electric energy and rationally utilizing power consumption

Inactive Publication Date: 2005-08-31
INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI
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Problems solved by technology

[0002] In the general motherboard design, the main frequency of the bus is also called the external frequency, which is generated by the frequency

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  • Dynamic frequency conversion device of bus in high speed and kermel interface of processor under SOC architecture
  • Dynamic frequency conversion device of bus in high speed and kermel interface of processor under SOC architecture
  • Dynamic frequency conversion device of bus in high speed and kermel interface of processor under SOC architecture

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[0019] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0020] Such as figure 1 In the shown high-speed bus dynamic frequency conversion device, the clock circuit 1 is conventional and generally consists of a phase-locked loop. The clock circuit 1 provides the processor core (not shown in the figure) with the main frequency CPUclk through the processor core interface 2.

[0021] In the present invention, the processor core main frequency CPUclk is also sent to the bus frequency generator 3 as the bus reference frequency, and the bus frequency generator 3 divides the processor core main frequency CPUclk to provide the bus frequency APBclk. Such as figure 1 As shown, the frequency selection register 4 stores the frequency division relationship value SD between the bus frequency APBclk and the processor core frequency CPUclk. Because of the need for synchronization across clock domains, the frequency divisi...

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Abstract

The present invention discloses a high-speed bus dynamic frequency conversion device under SOC structure and processor kernel interface. Said frequency conversion device includes clock circuit, bus frequency generator, frequency selective registor and synchronous clock. In the interior of frequency selective register a frequency-dividing relationship value is stored, after the frequency-dividing relationship value is synchronized by synchronous clock, it can be transferred into bus frequency generator to make signal frequency division, the clock circuit can provide bus reference frequency for bus frequency generator, and the bus freqency generator can be used for receiving frequency division signal to frequency-divide bus refrence frequency, then providing bus frequency. Said invention processor kernel interface includes a condition processor, said condition processor can receive working state signal of bus and processor kernel so as to control processor kernel to make bus operation.

Description

technical field [0001] The present invention relates to the field of CPU / SOC, more specifically, the present invention relates to the high-speed bus dynamic frequency conversion technology under the SOC framework. Background technique [0002] In general motherboard design, the main frequency of the bus is also called external frequency, which is generated by the motherboard frequency generator and controlled by jumpers. Once the frequency is changed, the system needs to be restarted, which lacks flexibility. [0003] However, in the field of SOC design, the main frequency of the bus is often associated with the main frequency of the processor core, and the conventional method is to divide the frequency by two. However, as the main frequency of the processor core is getting higher and higher, the bus frequency requirements of the SOC architecture are more flexible in order to adapt to the off-chip main frequency requirements. For example, the off-chip memory access is 100 or...

Claims

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Application Information

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IPC IPC(8): G06F1/04G06F13/00
Inventor 张志敏吴登峰
Owner INST OF COMPUTING TECHNOLOGY - CHINESE ACAD OF SCI
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