Loading method and device

Abstract

The embodiment of the invention provides a loading method and a device, the loading method comprises: a first certification information is received, after the match of the first certification information and a pre-stored second certification information succeeds, a configuration bus is connected with a configuration interface of a programmable logic device; the programmable logic device is loadedthrough the configuration bus. In the embodiment of the invention, before the programmable logic device is loaded, the certification operation is firstly conducted, only after the certification is qualified, the programmable logic device can be loaded, thereby effectively avoiding the incorrect loading of the programmable logic device, and increasing the reliability and stability of the embedded system.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a loading method and device. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array; hereinafter referred to as: FPGA) is developing rapidly. From the initial few thousand gates to the current several million gates, the reliability and integration level are continuously improved, while the power consumption and cost are continuously reduced. , has a very high cost performance, so it is widely used in embedded system design. Therefore, loading the FPGA correctly is of vital importance to ensure the reliability and stability of the entire embedded system. [0003] Correctly loading the FPGA is to configure the FPGA correctly after the FPGA is powered on, so that the FPGA can achieve the expected functions. However, if the FPGA is reloaded due to misoperation to the configuration bus during other operations, resulting in the FPGA not bein...

AI Technical Summary

Problems solved by technology

[0005] Using the above method to load the FPGA, once the timing of the cs, data, dclk and config signal lines changes, the FPGA will be misloaded, thereby modifying the internal wiring structure of the FPGA and affecting the stability of the embedded system

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