A limiting circuit
A limiting circuit and limiting technology, applied in the electronic field, can solve the problems of power supply voltage deviation and low precision
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Embodiment 1
[0029] figure 1 It is a schematic diagram of a limiter circuit according to an embodiment of the present invention, please refer to figure 1 :
[0030] A limiting circuit, comprising a voltage sampling unit 1, an amplifying unit 2 and a limiting unit 3, wherein the voltage sampling unit 1 generates a first bias current I through a bias current generating circuit 1 The sampling voltage is formed by flowing through the sampling resistor; the amplifying unit 2 amplifies the voltage drop formed between the power supply voltage and the sampling voltage; the limiting unit 3 limits the voltage amplified by the amplifying unit 2 .
Embodiment 2
[0032] figure 2 It is a schematic diagram of a limiter circuit in Embodiment 2 of the present invention, please refer to figure 2 :
[0033] In this embodiment, the voltage sampling unit includes a sampling resistor 11, the amplifying unit includes a PMOS amplifier tube P1 and a load circuit 21, the limiting unit includes an NMOS discharge tube N3, the sampling resistor 11 is connected to a bias current generation circuit, and the bias current generation circuit circuit generates a first bias current flow I 1 Flow through the sampling resistor 11 to form a sampling voltage, I1 flows into the gate of P1, one end of the sampling resistor 11 is connected to the gate of the PMOS amplifier P1, the other end of the sampling resistor 11 is grounded to VSS, and the source of the PMOS amplifier P1 is connected to the power supply VDD , the load circuit 21 is connected between the ground wire VSS and the drain of the PMOS amplifier P1, the drain of the PMOS amplifier P1 is connected...
Embodiment 3
[0038] In the following, the first switching control circuit includes a first NMOS control transistor, the second switching control circuit includes a second NMOS control transistor and a second inverter, and the sampling resistor 11 is an adjustable resistor R1 as an example. Please refer to image 3 , image 3 It is a schematic diagram of a limiter circuit in Embodiment 3 of the present invention:
[0039] The resistor R1 is connected to the bias current generating circuit, and the first bias current I generated by the bias current generating circuit flows 1 It flows into the gate of PMOS amplifier tube P1; one end of resistor R1 is connected to the gate of PMOS amplifier tube P1, the other end of resistor R1 is grounded to VSS, and the first bias current flows I 1 Flow through resistor R1 to form the sampling voltage. The source of the PMOS amplifier tube P1 is connected to the power supply VDD, and the drain is connected to the first load circuit; the first load circuit ...
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