Cache access methods, devices and processors

A technology for caching devices and access methods, applied in the computer field, can solve problems such as data access failure and data inability to obtain

Active Publication Date: 2019-03-05
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, when data is modified through one of the virtual addresses, the modified data is stored in the cache line corresponding to the index of the virtual address, and the modified data cannot be obtained through other virtual addresses, resulting in data access failure

Method used

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  • Cache access methods, devices and processors
  • Cache access methods, devices and processors
  • Cache access methods, devices and processors

Examples

Experimental program
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Embodiment Construction

[0032] It should be noted that each embodiment of the present invention is based on a cache consistency maintenance mechanism, and the mechanism is briefly introduced first. The cache coherence maintenance mechanism is a mechanism for maintaining cache coherence (English: cache coherence), which is especially common in multi-core processors. Even in a single-core processor, it is used to ensure the inclusion relationship of the lower-level cache to the upper-level cache. For example, Loongson 3 multi-core processors and Loongson 2G, 2H and other single-core processors have cache consistency maintenance mechanisms. The working principle of this mechanism is: when the first-level cache fails, it will access the second-level cache, and the second-level cache sends a consistent request to the first-level cache, for example, including requests such as invalidation, invalidation and writeback, and writeback only. These requests modify the first-level cache and achieve the purpose o...

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Abstract

The embodiment of the invention provides a cache access method and equipment and a processor. The method includes the steps that when first cache equipment confirms that a cache fails according to a first virtual address, the first cache equipment acquires bits, different from indexes of a second virtual address, in indexes of the first virtual address as a first page of coloring bits; a cache failure request is sent to second cache equipment, wherein the cache failure request comprises a first physical address and the first page of coloring bits, first data sent by the second cache equipment according to the cache failure request is received, data and identification corresponding to the indexes of the first virtual address are updated, therefore, it is guaranteed that access to latest data corresponding to the first physical address can be achieved according to the first virtual address, and the data access success rate is increased.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a cache access method, device and processor. Background technique [0002] When using memory to share data or communicate between multiple processes, there will be a mapping relationship in which multiple virtual addresses are mapped to the same physical address. In this case, multiple virtual addresses may be mapped to cache (English: cache) Multiple indexes (English: index) of multiple indexes (English: index), so that the data stored corresponding to the corresponding index can be obtained from the cache according to the virtual address. Since the data stored corresponding to multiple indexes in the cache is the same data, through the multiple The virtual address can obtain the same data, so that data sharing between multiple processes can be realized. [0003] However, when data is modified through one of the virtual addresses, the modified data is stored in the ca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/128
Inventor 吴瑞阳郝守青汪文祥胡伟武
Owner LOONGSON TECH CORP
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