Method for improving statistical analysis efficiency of functional coverage through assertions and script

Abstract

The invention provides a method for improving statistical analysis efficiency of functional coverage through assertions and a script, belongs to the field of integrated circuit verification technology and aims to solve the problems that in the prior art, when a simulation tool is used to perform statistical analysis on the functional coverage, time and labor are wasted, and iteration is not easy. According to the adopted technical scheme, functional points are included into a file through statistical analysis after being generalized according to rules, the assertions are added in design, log information is processed by use of the text processing ability of the script, and real-time statistical analysis of coverage data is realized. The method comprises the specific steps that (1) the functional points are described regularly, subjected to statistical analysis and written into the file; (2) the assertions corresponding to the functional points are added in design according to the functional point description rules, the functional points with the successful assertions are described into a unified assertion report; and (3) the scrip running concurrently with a verification environment is developed, whether assertion report content is changed is monitored in real time, the changed assertion report content is recorded, and the coverage is given when current case simulation is ended. Through the method, the coverage data can be subjected to real-time statistical analysis.

Description

technical field [0001] The invention relates to the technical field of integrated circuit verification, in particular to a method for improving the coverage efficiency of statistical functions by using assertions and scripts. Background technique [0002] Today's integrated circuits are large in scale, complex in logic and algorithms, and difficult to verify. Often a design needs to use several verification methods or verification ideas to make the design verification relatively sufficient. The judgment of whether the design function verification is sufficient generally depends on the functional coverage. . In the design verification process, the design may add or delete functions, verify iterations, and develop new test cases. Large designs may have hundreds or thousands of test cases. In this case, if the artificial statistical function coverage , it has the disadvantages of error-prone and low efficiency. If purely relying on simulation tools to count function coverage, ...

AI Technical Summary

Problems solved by technology

[0002] Today's integrated circuits are large in scale, complex in logic and algorithms, and difficult to verify. Often a design needs to use several verification methods or verification ideas to make the design verification relatively sufficient. The judgment of whether the design function verification is sufficient generally depends on the functional coverage.

In the design verification process, the design may add or delete functions, verify iterations, and develop new test cases. Large designs may have hundreds or thousands of test cases. In this case, if the artificial statistical function coverage , it has the disadvantages of error-prone and low efficiency. If purely relying on simulation tools to count function coverage, it will first occupy a considerable amount of system resources. Secondly, it is not easy to collect the coverage results of all test cases. When developing new When testing the test cases, it is necessary to analyze which ones have been covered. After the test is completed, it is necessary to use tools to integrate this part of the coverage data into the existing database. Finally, if in the iterative stage, design modifications or function deletions occur , it will take a lot of time to re-count