Manufacturing method of array substrate

Abstract

A method for manufacturing an array substrate includes providing a substrate on which a planarization layer is formed, the planarization layer including first vias; forming transition layers in the first vias; forming a first patterned transparent electrode layer and a patterned passivation layer both of which expose the transition layers; and etching to remove the transition layers. According tothe method for manufacturing an array substrate, the transition layers are formed in the vias in the planarization layer, via fall can be reduced, so that no light resistance remains in the vias in the process of forming the first patterned transparent electrode layer, thereby avoiding the circumstance that transparent electrode material residual in the vias exists and causing occurrence of blindholes in the subsequent manufacturing process.

Description

technical field [0001] The present invention relates to the technical field of display, in particular to a manufacturing method of an array substrate. Background technique [0002] With the development of display technology, liquid crystal display panels (Liquid Crystal Display, LCD) are more and more popular due to their advantages of lightness and low radiation. The liquid crystal display panel includes an opposing color filter substrate (ColorFilter, CF) and a thin film transistor array substrate (TFTarray), and a liquid crystal layer (LC layer) sandwiched between them. [0003] Figure 1A to Figure 1E It is a schematic cross-sectional view of various steps in a conventional manufacturing method of an array substrate. Such as Figure 1A to Figure 1E As shown, the existing production method comprises the following steps: [0004] exist Figure 1A Among them, a first passivation layer (PV) 11 is provided on the substrate (not shown), a planarization layer 12 is formed on...

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Problems solved by technology

[0008] exist Figure 1E In the process, the transparent conductive layer 13 is etched to obtain a patterned transparent electrode layer 13, so that the part of the transparent electrode layer 13 corresponding to the via hole 121 exposes the lower first passivation layer 11, but due to the remaining light in the via hole 121 The resist 141 covers part of the transparent conductive layer 13, resulting in that this part of the transparent conductive layer 131 is not completely etched away during the etching process, and remains in the via hole 121.

[0009] In the subsequent process, when it is necessary to etch and remove the portion corresponding to the via hole 121 on the first passivation layer 11 to expose the underlying conductive layer (not shown), since the first passivation layer 11 adopts dry etching ( DET) method to remove, and the dry etching method has an extremely low etch rate to ITO, that is, the etch rate to the remaining transparent conductive layer 131 is extremely low, which will cause the first passivation layer 11 on this position to be completely etched away. Blind holes appear, which in turn leads to the problem of poor bonding of subsequent electrodes

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