Instruction out-of-order execution method, processor and electronic equipment

Abstract

The invention discloses an instruction out-of-order execution method, a processor and electronic equipment. The method comprises steps of allocating an index tag to the received instruction through the scoreboard, wherein each instruction has a specific tag; preferentially sending the instructions without structural risks and read-write risks to an arithmetic unit for execution, sending an operation result to a reorder cache, and after a delivery condition is met, delivering the result to a target register according to an index tag sequence to realize out-of-order execution and in-order delivery of the instructions. According to the method and the device, the scoreboard is matched with the reordering cache, so that write-read risks and write risks in data risks are eliminated, the application scene of out-of-order execution is expanded, the utilization rate of an arithmetic unit is increased, the overall speed of instruction execution is increased by reducing the waiting time of instruction execution, and the hardware cost is reduced.

Description

technical field [0001] The invention relates to the field of processor instruction execution, in particular to a method for instruction out-of-order execution, a processor and electronic equipment. Background technique [0002] In a computer system that executes sequentially, different instructions require different times, and the arithmetic unit may be empty during the waiting process. In order to improve the operating efficiency of computer programs, people need an overall optimization method to dynamically schedule the execution of instructions and complete the execution in the shortest time. Out-of-order execution can reduce the waiting time of the operation unit, but it may cause the reading and writing of data to violate the order of the original instructions, that is, data hazards occur, and the operation results of the instructions do not meet expectations. The existing common way to eliminate Write-After-Read Hazard and Write-After-Write Hazard is register renaming...

AI Technical Summary

Problems solved by technology

Out-of-order execution can reduce the waiting time of the operation unit, but it may cause the reading and writing of data to violate the order of the original instructions, that is, data hazards occur, which makes the operation results of the instructions not meet expectations

The existing common way to eliminate Write-After-Read Hazard and Write-After-Write Hazard is register renaming (Register Renaming), but the additional registers required in this way will cause Increases in chip complexity, area and power consumption

Images