Multi-serial port IP (Internet Protocol) core based on Avalon-MM (Multi-Media) bus interface

A bus interface and multi-serial port technology, applied in the field of multi-serial port IP cores, can solve the problems of small IP core FIFO depth, wasting ARM interrupt resources, affecting application process, etc., to save interrupt resources, occupy less resources, and design flexible and convenient Effect

Inactive Publication Date: 2020-05-29
NO 717 INST CHINA MARINE HEAVY IND GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The common way to realize the serial port on the FPGA side is to call the UART IP core provided by the SOC manufacturer, such as the UART 16550 IP core of Xilinx. The UART 16550 IP core has an AXI interface and an interrupt output port and can be directly connected to the ARM. The depth is small (the depth is only 16, and the width is 8), and multiple interruptions will be generated when a large amount of data is received at one time; especially when using multiple serial port modules, it is necessary to add multiple IP cores to the system, each IP interrupt Both are connected to the ARM side, which not only wastes ARM interrupt resources but also seriously affects the application process

Method used

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  • Multi-serial port IP (Internet Protocol) core based on Avalon-MM (Multi-Media) bus interface
  • Multi-serial port IP (Internet Protocol) core based on Avalon-MM (Multi-Media) bus interface
  • Multi-serial port IP (Internet Protocol) core based on Avalon-MM (Multi-Media) bus interface

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Embodiment

[0033] Such as figure 1 figure 2 As shown, the embodiment of the present invention provides a kind of multi-serial port IP core based on Avalon-MM bus interface, adopts hardware description language Verilog to design, comprises ARM side communication interface unit, storage unit and serial data input and output interface unit;

[0034] The ARM side communication interface unit includes an Avalon-MM bus interface module and an interrupt output interface module, the Avalon-MM bus interface module realizes the data exchange from the ARM side to the FPGA side through a bus transfer interface, and the interrupt output interface module uses Used to output interrupt signal to ARM;

[0035] The serial data input and output interface unit includes 8 serial ports, which are used to realize the data interaction between the external equipment and the storage unit;

[0036] Described storage unit comprises 3 global registers and 8 register modules, and described 8 register modules corre...

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Abstract

The invention relates to a multi-serial port IP core based on an Avalon-MM bus interface, which is designed by adopting a hardware description language Verilog, and comprises: an Avalon-MM bus interface module used for realizing data exchange from an ARM side to an FPGA side; eight serial ports which are used for realizing data interaction between external equipment and the storage unit; three glolal registers and eight register modules, wherein the eight register modules are respectively corresponding to the eight serial ports of the serial data input / output interface unit, and the three global registers are respectively in communication connection with the eight register modules through FPGA internal buses. The Avalon-MM has independent write data lines, read data lines and address lines, and has the advantages of reading effective signals, occupying less resources and the like, eight serial ports are realized in an addressing mode, and the eight serial ports share one interrupt, sothat interrupt resources are greatly saved.

Description

technical field [0001] The invention relates to the technical field of serial port communication, in particular to a multi-serial port IP core based on an Avalon-MM bus interface. Background technique [0002] In an inertial navigation device, the serial port is the main interface for communication between the device and the outside world. An inertial navigation device may have more than a dozen serial ports. These serial ports are mostly implemented by the navigation computer in the device. The core of the navigation computer is the SOC chip integrating FPGA and ARM. The serial port is realized on the FPGA side, and the ARM realizes the read, write and control operations of the serial port on the FPGA side through the AXI bus. [0003] When the device sends data to the outside, the ARM writes the sent data into each serial port in the FPGA through the AXI bus, and the FPGA serial port completes the data parallel-to-serial conversion and sends it out; when the outside sends ...

Claims

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): G06F13/24G06F13/42
CPCG06F13/24G06F13/4291
Inventor杨伟新尹业宏郑畅彭煜陈国庆
OwnerNO 717 INST CHINA MARINE HEAVY IND GRP