Chip comprising multiply accumulator, terminal and floating point operation control method

Abstract

The invention discloses a chip comprising a multiply accumulator, a terminal and a floating point operation control method, and relates to the field of chips. The multiply accumulator comprises a floating point number input end, a first selection end, a floating point general unit and an output unit, wherein the floating point universal unit is connected with the floating point number input end, the first selection end and the output unit. According to the invention, in different floating point operation modes, the floating point number with high bit width can be split into sub-operands with low bit width to carry out multiply-accumulate operation, and according to the selecting of a floating point operation mode, the multiplier and the adder in the multiply accumulator are controlled to be split and recombined, so that the operational circuit in the multiply-accumulator becomes an operational circuit corresponding to the floating-point operation mode, the operational circuit can support multiply-accumulate operation of floating-point numbers with different bit widths, at least two sets of hardware structures do not need to be integrated on the chip, and the area and power consumption of the chip are effectively reduced.

Description

technical field [0001] The present application relates to the field of chips, in particular to a chip including a multiply accumulator, a terminal and a control method for floating-point operations. Background technique [0002] The multiplier-accumulator used for floating-point calculation is used as a basic calculation unit, such as a graphics processing unit (Graphics Processing Unit, GPU), an artificial intelligence (Artificial Intelligence, AI) chip, a central processing unit (Central Processing Unit, CPU), on-site Core components on chips such as Field-Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC). [0003] FP16, FP32, FP64 and other bit-width floating-point operations need to use different hardware structures. For example, FP64 floating-point operations use a set of hardware structures, FP16 floating-point operations and FP32 floating-point operations use a set of hardware structures, and two sets of hardware structures independen...

AI Technical Summary

Problems solved by technology

[0004] Therefore, for the multiplication operation of the decimal part, FP16 floating-point operation and FP32 floating-point operation use independent operation circuits, and it is still necessary to integrate a lot of operation units on the chip to support the floating-point operation of the above two types of operation bit width at the same time. , resulting in a large chip area and power consumption

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