Method and device for stabilizing writing speed of flash memory, storage medium and computer equipment

A technology for flash memory storage and writing speed, which is applied in the field of a method, device, storage medium and computer equipment for stabilizing the writing speed of flash memory, which can solve the problems of flash memory writing data slowdown, etc., and achieve the effect of stabilizing the writing speed

Active Publication Date: 2021-05-07
SHENZHEN DEMINGLI ELECTRONICS
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] The main purpose of the present invention is to provide a method for stabilizing the writing speed of flash memory, aiming at solving the technical problem of speed drop when writing data in flash memory

Method used

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  • Method and device for stabilizing writing speed of flash memory, storage medium and computer equipment
  • Method and device for stabilizing writing speed of flash memory, storage medium and computer equipment
  • Method and device for stabilizing writing speed of flash memory, storage medium and computer equipment

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Embodiment Construction

[0049] It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0050] refer to figure 1 and figure 2 , the present invention provides a method for stabilizing flash memory write speed, comprising:

[0051] S1: Set the specified storage unit in the first flash memory to SLC mode as an SLC buffer block, wherein the first flash memory includes all flash memory in the flash memory storage device, and the first flash memory includes TLC units or QLC units;

[0052] S2: Obtain the data transfer time and programming time required for a single write to the first flash memory;

[0053] S3: According to the data transmission time and programming time, calculate the number of flash memory cells required to write data in the flash memory without slowing down;

[0054] S4: sort the number of flash memory units in sequence, and write data into each flash memory unit in a preset order from ...

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Abstract

The invention discloses a method and device for stabilizing the writing speed of a flash memory, a storage medium and computer equipment, and the method comprises the steps of setting a specified data block in a first flash memory as an SLC mode, and taking the specified data block as an SLC buffer block; acquiring data transmission time and programming time required for writing in the first flash memory for one time; according to the data transmission time and the programming time, calculating the number of flash memory units needed by flash memory data writing; sequentially sequencing flash memory units according to a certain number, writing data into each flash memory unit according to a preset sequence from the first flash memory unit, so that the data transmission time of the next flash memory unit is parallel to the programming time of the previous memory unit; and after monitoring that the previous flash memory unit has idle time, switching the flash memory unit to the previous flash memory unit in time to start background data arrangement operation, so that the SLC cache block of the previous flash memory unit can be released in time, and the situation that the flash memory unit cannot write data when the SLC cache block is used up, so that the writing speed of the flash memory is suddenly reduced can be avoided.

Description

technical field [0001] The invention relates to the field of flash memory, in particular to a method, device, storage medium and computer equipment for stabilizing the writing speed of flash memory. Background technique [0002] A single write operation of flash memory generally includes two parts: first, the data to be written is transferred to the internal cache of the flash memory, and second, the flash memory programs the data in the internal cache and solidifies it in the internal storage unit of the flash memory. The time spent on this part is usually Called programming busy time. For the new TLC (Trinary-Level Cell, three-level storage unit) flash memory and QLC (Quad-Level Cell, four-level storage unit), the programming busy time is as long as 1ms or more. [0003] For high-speed host (host) interfaces such as SATA (Serial Advanced Technology Attachment hard disk, SATA hard disk), PCIE (peripheral component interconnect express, high-speed serial computer expansion ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10
CPCG11C7/1042G11C7/1084Y02D10/00
Inventor 李国强
Owner SHENZHEN DEMINGLI ELECTRONICS
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