A high-speed 8/9 prescaler circuit, its control method and its phase-locked loop

A control method and dual-mode prescaler technology, applied in the direction of automatic power control, electrical components, etc., can solve the problem that the operating frequency is greatly affected by the power supply voltage

A control method and dual-mode prescaler technology, applied in the direction of automatic power control, electrical components, etc., can solve the problem that the operating frequency is greatly affected by the power supply voltage

CN112953525BActive Publication Date: 2022-03-11SOUTH CHINA UNIV OF TECH

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A high-speed 8/9 prescaler circuit, its control method and its phase-locked loop
  • A high-speed 8/9 prescaler circuit, its control method and its phase-locked loop
  • A high-speed 8/9 prescaler circuit, its control method and its phase-locked loop

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] Below in conjunction with accompanying drawing, illustrate the embodiment of the present invention.

[0023] The dual-mode prescaler based on CML logic and the dual-mode prescaler based on TSPC logic both have digital frequency dividers and can work in a wide frequency range. From the perspective of power consumption and area, the dual-mode prescaler based on TSPC logic The frequency converter is generally the first choice. The dual-mode 8 / 9 prescaler based on the TSPC latch provided by the present invention has high operating frequency and wide frequency coverage.

[0024] The overall circuit of the present invention is as figure 2 As shown, including TSPC first type latches L1, L3, L5, L7, L9, TSPC second type latches L2, L4, L6, L8, L10, NAND gate G2, NOR gate G3 and NOT gate G1, G4.

[0025] When the TSPC first type latches L1, L3, L5, L7, L9 are at high level, the output of the first type latch is equal to the input of the first type latch, and at low level, th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a high-speed 8 / 9 dual-mode prescaler, comprising 10 TSPC latches L1‑L10, 1 NAND gate (G2), 1 NOR gate (G3), a first NOT gate (G1) and the second NOT gate (G4); it is characterized in that: TSPC latches L1, L3, L5, L7 and L9 are first type latches, TSPC latches L2, L4, L6, L8 and L10 for the second type of latch. The high-speed 8 / 9 dual-mode prescaler proposed by the invention has high operating frequency and wide frequency band coverage.

Description

technical field [0001] The present invention relates to the field of high-speed analog circuits and radio frequency integrated circuits, in particular, to a dual-mode prescaler circuit, and more specifically, to a high-speed 8 / 9 prescaler circuit and its control method and including the Phase-locked loop for prescaler. Background technique [0002] In the phase-locked loop, the prescaler is often used as a part of the frequency divider to figure 1 The pulse-swallowing programmable frequency divider that is common in China is an example. The dual-mode 8 / 9 prescaler is used to divide the high-frequency signal output by the oscillator in the phase-locked loop to a lower frequency, and then input it to other programmable frequency dividers. In the frequency function module, the frequency divider can realize the frequency division ratio: 8×M+A, where M is the modulus value of the M counter, A is the modulus value of the A counter, and both M and A are integers. [0003] Commonl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
11 Mar 2022
Publication
CN112953525B
IPC
H03L7/099
CPC
H03L7/099
Inventors
陈志坚; 吴子莹