Method and device for optimizing digital logic circuit layout and storage medium

Abstract

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: dividing a layout diagram of the digital logic circuit into a plurality of cells, each cell comprises a plurality of elements, determining to-be-optimized elements in the cells based on the current layout and an optimization target of the digital logic circuit, and optimizing the layout of the digital logic circuit according to the to-be-optimized elements. The optimization target comprises at least one of a line length target, a congestion target or a density target, obtaining a target density function value according to the target model based on the layout characteristics of the cells, and adjusting the position of the element to be optimized in the cells based on the target density function value so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, labor time and cost are saved, and the performance of a chip is further improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device and storage medium for optimizing the layout of digital logic circuits. Background Art

[0002] Electronic design automation (EDA) software is widely used in chip design. With the help of various EDA software, engineers can easily carry out chip design, such as architecture design and register transfer level (RTL) code design, synthesis, design for test (DFT), physical development and signoff.

[0003] In the process of chip design using EDA software, high-quality circuit layout and routing is a prerequisite for successful chip design, and complex and time-consuming layout planning is the key to achieving high-quality layout and routing. Modern industrial layout methods require engineers to perform layout and routing manually or rely on empirical rules, which is time-consuming and difficult to guarantee the effect. At the same time, as the scale of modern digital logic circuits becomes larger and the functions become more complex, users have higher and higher requirements for the timing, power consumption or area (Performance Power Area, PPA) of the circuit. Only by placing each component in the chip in the right position can the required timing, power consumption or area be achieved.

[0004] Therefore, how to optimize the layout of digital logic circuits is an urgent problem to be solved in the industry. Summary of the invention

[0005] In view of this, the purpose of the present application is to propose a method, device and storage medium for optimizing the layout of digital logic circuits to solve or partially solve the above-mentioned problems.

[0006] Based on the above-mentioned purpose, in a first aspect, the present application provides a method for optimizing the layout of a digital logic circuit, the method comprising: dividing the layout diagram of the digital logic circuit into a plurality of cells, each cell comprising a plurality of components; determining the components to be optimized in the cells based on the current layout and optimization target of the digital logic circuit, the optimization target comprising at least one of a line length target, a congestion target or a density target; obtaining a target density function value according to a target model based on the layout characteristics of the cells; and adjusting the position of the components to be optimized in the cells based on the target density function value to optimize the layout of the digital logic circuit.

[0007] In a second aspect of the present application, a computer device is provided, including: One or more processors, memory; and one or more programs; The one or more programs are stored in the memory and executed by the one or more processors, the programs comprising instructions for executing the method according to the first aspect.

[0008] According to a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method according to the first aspect.

[0009] From the above, it can be seen that the present application provides a method, device and storage medium for optimizing the layout of digital logic circuits, by dividing the layout diagram of the digital logic circuit into multiple cells, each cell includes multiple components, based on the current layout and optimization target of the digital logic circuit, determining the components to be optimized in the cell, the optimization target includes at least one of the line length target, congestion target or density target, based on the layout characteristics of the cell, obtaining the target density function value according to the target model, based on the target density function value, adjusting the position of the components to be optimized in the cell to optimize the layout of the digital logic circuit. Through the method of the present application, automatic layout optimization of digital logic circuits can be achieved, saving labor time and cost, and further improving the performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of an exemplary computer device according to an embodiment of the present application is shown.

[0012] Figure 2 A basic structural diagram of a simulation tool according to an embodiment of the present application is shown.

[0013] Figure 3 A flow chart of a design and manufacturing process of an exemplary chip according to an embodiment of the present application is shown.

[0014] Figure 4 A schematic diagram showing an exemplary application scenario according to an embodiment of the present application is shown.

[0015] Figure 5 A schematic diagram showing an exemplary initial layout according to an embodiment of the present application is shown.

[0016] Fig. 6A A schematic diagram for optimizing the layout of a digital logic circuit according to an embodiment of the present application is shown.

[0017] Figure 6B A schematic diagram of exemplary congestion-targeted layout optimization according to an embodiment of the present application is shown.

[0018] Figure 6C A schematic diagram of exemplary density-targeted layout optimization according to an embodiment of the present application is shown.

[0019] Fig.6D and Fig. 6E A schematic diagram for optimizing the layout of a digital logic circuit according to an embodiment of the present application is shown.

[0020] Figure 7 A flowchart of an exemplary method for optimizing the layout of a digital logic circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] As mentioned above, in the process of chip design using EDA software, high-quality circuit layout and routing is a prerequisite for successful chip design, and complex and time-consuming layout planning is the key to achieving high-quality layout and routing. The layout method in the modern industry requires engineers to perform layout and routing manually or rely on empirical rules, which is time-consuming and the effect is difficult to guarantee. At the same time, as the scale of modern digital logic circuits becomes larger and larger, and the functions become more and more complex, users have higher and higher requirements for the timing, power consumption or area of ​​the circuit. Only by placing each component in the chip in the appropriate position can the desired timing, power consumption or area be achieved. The current layout optimization method often limits the improvement of the chip in terms of timing, power consumption or area.

[0024] Therefore, how to optimize the layout of digital logic circuits is an urgent problem to be solved in the industry.

[0025] In order to at least solve the above problems, the present application provides a method, device and storage medium for optimizing the layout of digital logic circuits, by dividing the layout diagram of the digital logic circuit into multiple cells, each cell includes multiple components, based on the current layout and optimization target of the digital logic circuit, the components to be optimized in the cell are determined, the optimization target includes at least one of the line length target, congestion target or density target, based on the layout characteristics of the cell, the target density function value is obtained according to the target model, based on the target density function value, the position of the component to be optimized in the cell is adjusted to optimize the layout of the digital logic circuit. Through the method of the present application, automatic layout optimization of digital logic circuits can be achieved, saving labor time and cost, and further improving the performance of the chip.

[0026] Figure 1 A schematic diagram of an exemplary computer device 100 according to an embodiment of the present application is shown, and the device 100 may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other in communication within the device through the bus 1050.

[0027] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0028] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0029] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0030] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0031] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0032] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0033] Figure 2 A basic structural diagram of a simulation tool 200 according to an embodiment of the present application is shown.

[0034] like Figure 2 As shown, the part above the dotted line is the user part; the part below the dotted line is the simulation tool 200, which can be Figure 1The device 100 shown is implemented. The simulation tool 200 may include a Tcl command (or a graphic / window interface) module 204, various calculation modules (e.g., a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.) and a database system 212. The user 202 may operate the simulation tool 200 by inputting relevant commands in the Tcl command (or graphic / window interface) module 204. In some embodiments, the simulation tool 200 may be any EDA (Electronic Design Automation) software.

[0035] The Tcl command module 204 mainly performs the functions of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific contents of the instructions.

[0036] According to different computing tasks, each computing module can be divided into, for example, a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization computing module 210 can be used to optimize the placement position and wire connection method between each component. The computing process of these computing modules can be, for example, Figure 1 is performed in the processor 102.

[0037] The database system 212 can be used to completely and comprehensively record and store all information of the simulated or designed chip (such as position, direction, size, structure, wire connection method, etc.), for example, stored in Figure 1 The database system 212 may include database systems from different perspectives, for example, Figure 2 As shown, database system (schematic perspective) 2122 and database system (memory perspective) 2124.

[0038] Figure 3 A flow chart of an exemplary chip design and manufacturing process 300 according to an embodiment of the present application is shown.

[0039] like Figure 3As shown, the design and manufacturing process 300 starts with specification formulation 302. In the stage of specification formulation 302, the requirements for the functions and performances that the integrated circuit (i.e., digital logic circuit) needs to achieve are determined. In the stage of chip design 304, circuit design is performed with the help of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference of the circuit (e.g., digital circuit or analog circuit), the design 304 may include different design links. In the stage of manufacturing 306, integrated circuits are formed on wafers through processes such as lithography, etching, ion implantation, thin film deposition, and polishing. In the stage of packaging 308, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The obtained chip is tested in the stage of testing 310 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 302. The qualified chip 312 can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present application. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out can be performed before manufacturing 306. A small number of chips from the tape-out can be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0040] In some embodiments, the design 304 of the digital logic circuit may exemplarily include an architecture design 322, an RTL design 324, a functional simulation 326, a synthesis 328, a timing analysis 330, a DFT 332, a verification check 334, a layout 336, a design rule check (DRC) 338, and a layout generation 340. The architecture design 322 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the types and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 324, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 326 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 328 may convert RTL into a gate-level netlist. Synthesis 328 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0041] Timing analysis 330 is usually static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. In the DFT 332 stage, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). In the verification check 334 stage, the circuit can be formally verified and / or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theory prover. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between the gate-level netlist and the gate-level netlist.

[0042] In the stage of layout and routing 336, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 328 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing usually expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of this application. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0043] At the DRC 338 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 340 by the EDA software. It can be understood that the above links are only exemplary and not intended to limit the scope of this application. In the actual design process, the above links can be added, deleted or modified according to design needs. In addition, some of the above links can be implemented by different EDA software or integrated in one or more EDA software. This application does not limit this.

[0044] The scheme for optimizing the layout of digital logic circuits of the present application can be applied to the physical synthesis stage in the synthesis 328 stage. The components of the circuit layout planning include the layout of macro cells and standard cells. Macro cells mainly include storage cells and various custom cells, which are the main functional modules of digital logic circuits. Standard cells are modules of underlying electronic logic functions, such as various gate devices, triggers, latches and buffers.

[0045] After the macrocells are placed in the circuit layout, the performance, power consumption and area required by the circuit are achieved according to the design constraints of the circuit, such as layout rules and routing rules. It can be understood that the solution of the present application can also be applied to other scenarios of optimizing other circuits, and the present application does not limit this.

[0046] It is to be understood that, although each operation is described in a specific order above, this should be understood as not being limited to requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0047] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0048] Figure 4 A schematic diagram of an exemplary application scenario 400 according to an embodiment of the present application is shown.

[0049] like Figure 4As shown, the application scenario 400 may include a computer device 100. In some embodiments, the computer device 100 may be a device with computing functions such as a personal computer, a workstation, a server, etc. The process described in this application can be implemented by EDA tool software in an electronic device with computing functions such as a personal computer, a workstation, a server, etc. The computer device 100 may be installed with EDA software. During the EDA design process of the chip, a user (not shown) may input a configuration into the EDA software, and the EDA software may automatically generate a digital logic circuit. EDA software includes, but is not limited to, chip design auxiliary software, programmable chip auxiliary design software, and system design auxiliary software. The scope of this application is not limited in this respect.

[0050] The computer device 100 can obtain an initial layout 402 of a digital logic circuit, and the initial layout 402 of the circuit can include relative positions of devices (e.g., macrocells) in the circuit. In some embodiments, the computer device 100 can obtain a layout file for implementing the circuit and a netlist file representing the circuit as input to determine the initial layout 402 of the circuit. The layout file can be provided to the computer device 100, for example, in the form of a Graphic Design System (GDS) file. As an optional embodiment, the initial layout 402 of the circuit can also be provided directly to the computer device 100.

[0051] After obtaining the initial layout 402, the computer device 100 can determine the components to be optimized on the digital logic circuit according to the initial layout 402 and the specific optimization target. For example, the components to be optimized may include macro cells and standard cells. In some embodiments, the computer device 100 can determine the components to be optimized according to at least one of a timing target, a wire length target, a congestion target, or a density target.

[0052] After determining the components to be optimized, the computer device 100 can adjust the positions of the components to be optimized according to the design constraints of the circuit, such as the density function value, to obtain the target layout 406 of the circuit. In some embodiments, the computer device 100 can swap the positions of the macro cells or standard cells to be optimized to obtain the target layout 406 of the circuit. As an optional embodiment, the computer device 100 can change the positions of the macro cells or standard cells to be optimized to obtain the target layout 406 of the circuit.

[0053] Figure 5 A schematic diagram of an exemplary initial layout 402 according to an embodiment of the present application is shown.

[0054] like Figure 5As shown, in some embodiments, the computer device 100 may determine the design information of the digital logic circuit based on the netlist file 502 and the layout file 510 of the digital logic circuit, and then determine the initial density function value of the digital logic circuit based on the design information. The layout diagram of the digital logic circuit is divided into multiple regions 508 based on the initial density function value to obtain the initial layout 402. The multiple regions 508 may be cells of the same size. Each region 508 may include multiple first components 504, which may include macro cells and standard cells.

[0055] The netlist file 502 is also called a connection list, which is a description of the connection of a digital logic circuit. The netlist usually conveys information about the circuit connection, such as module instances, wire nets, and related properties. The layout file 510 may include the location and length and width of each first component 504 and the size of the area that can be laid out.

[0056] The design information may include at least one of area utilization, macrocell utilization, or channel utilization. In some embodiments, the computer device 100 may determine at least one of the area utilization, macrocell utilization, or channel utilization based on the netlist file 502 and the layout file 510 to obtain the initial layout 402. The area utilization refers to the size of the area occupied by the components in the digital logic circuit, which may be used to indicate the ratio of the available, blank area in the digital logic circuit. The macrocell utilization refers to the size of the area occupied by the macrocell in the digital logic circuit. The channel utilization refers to the size of the area occupied by the region between multiple macrocells in the digital logic circuit.

[0057] like Figure 5 As shown, there may be overlapping elements in the plurality of first elements 504 in the initial layout 402, and the placement positions of the plurality of first elements 504 are relatively concentrated in one area at the beginning, for example, the plurality of elements are relatively concentrated in the area 506. Therefore, in some embodiments, the initial density function value determined based on the design information can be set to a larger value, so that the size of the plurality of areas 508 divided based on the larger initial density function value will also be larger, so that the elements that can be placed in each area 508 will not overlap and will not be relatively concentrated in one area.

[0058] In the layout optimization stage of chip design, in some embodiments, the components in each area 508 can be optimized based on the initial layout 402 and the optimization target on the basis of the initial layout 402, so as to obtain an optimized layout. Then, the computer device 100 can, on the basis of the optimized layout, re-divide the layout diagram of the digital logic circuit into a plurality of cells smaller than the area 508 in size, so that the accuracy of the component layout optimization is gradually improved from coarse to fine. Furthermore, the component layout in each cell is further optimized based on the current layout and the division of the cells. The present application will be described below by taking the layout optimization based on the current layout of the digital logic circuit as an example. However, the scheme for optimization based on the initial layout should also be included in the scope of protection of the present application.

[0059] Fig. 6A FIG. 6 is a schematic diagram showing an exemplary method for optimizing a digital logic circuit layout 600 according to an embodiment of the present application.

[0060] like Fig. 6A As shown, the computer device 100 may obtain a target density function value according to the target model based on the layout characteristics of the first cell 604 in the current layout 600, and then adjust the position of the components to be optimized in the first cell 604 among the plurality of second components 602 according to the target density function value to optimize the layout 600. In some embodiments, the computer device 100 may determine the components to be optimized in each first cell 604 based on the current layout 600 of the digital logic circuit and the optimization target. The optimization target may include at least one of a line length target, a congestion target, or a density target.

[0061] Figure 6B A schematic diagram of exemplary congestion-targeted layout optimization according to an embodiment of the present application is shown.

[0062] like Figure 6B As shown, when the layout optimization is performed with congestion as the goal, in some embodiments, the computer device 100 can identify the congested area 612 where the components in the current layout 600 overlap, and then determine the components contained in the congested area 612 as the congested components to be optimized. As an optional embodiment, the computer device 100 can also determine whether there are congested components based on the distance between multiple components, such as the distance between the third component 614 and the fourth component 616. At the same time, the computer device 100 can also use the extracted congested components as the layout features of the first cell 604, obtain the target density parameters based on the target model and the layout features, and then obtain the target density function value for optimizing the cell layout based on the target density parameters. The target density function value can be used to adjust the position of the components to be optimized to avoid overlapping of the components.

[0063] Figure 6CA schematic diagram of exemplary density-targeted layout optimization according to an embodiment of the present application is shown.

[0064] When performing layout optimization with density as a goal, in some embodiments, the computer device 100 may identify the density of components in each cell in the current layout 600, for example, Figure 6C As shown, the component density of the second cell 622 can be the ratio of the area of ​​the fifth component 624 to the area of ​​the second cell 622. Then, the components in the cell with a larger component density are used as the components to be optimized. At the same time, the computer device 100 can also use the extracted component density as the layout feature of the cell, obtain the target density parameter based on the target model and the layout feature, and then obtain the target density function value for optimizing the layout of the cell with a larger component density based on the target density parameter. The target density function value can be used to adjust the position of the component to be optimized so that the relatively dense components become loose.

[0065] It should be noted that this embodiment is only described by optimizing the layout of components in cells with a larger density of components. However, when density is used as the optimization target, it is not limited to optimizing the layout of components with a larger density. The density of components in a digital logic circuit should not be too large or too small. Therefore, the solution of optimizing the layout of components with a smaller density using this embodiment should also be included in the protection scope of this application.

[0066] Density parameters play an important role in density-related objective functions, where the sum of the density functions of each cell can be the density function value of the entire digital logic circuit, and the placement of components in each cell will be gradually pushed out through the density function. Therefore, in the layout optimization process of chip design, the density function value can be the goal of layout optimization.

[0067] In addition, the setting of density parameters has a great impact on the results of component layout and total line length. If it is set too small, the components will be placed more dispersed, resulting in a poor total line length. If it is set too large, local components will not be able to spread out, resulting in greater local congestion. In traditional layout optimization, a fixed density parameter is set through manual experience for optimization, which is not universal enough and cannot achieve a more optimized goal on all chip layouts.

[0068] To at least solve the above problems, when the density function value or line length is used as the target of layout optimization, in some embodiments, the computer device 100 can also extract at least one of the density parameters or density function values ​​of the components in the cell in the current layout 600 as the layout feature of the cell. The target density parameter or target density function value obtained based on the target model can be used to update the current density parameter or density function value. The computer device 100 can use the target density parameter or target density function value obtained based on the target model to perform multiple iterations at a certain frequency on the current density parameter or density function value. This application is not limited to this. Multiple iterations can obtain more accurate density parameters or density function values.

[0069] The target model can be a deep neural network model built based on an image model and a sequence model. Taking into account that the layout features of digital logic circuits may include image data and sequence data, in some embodiments, when training a pre-built target model, at least one of the congested component data or component density data of a cell can be used as image data, and at least one of the density parameter data or density function data can be used as sequence data, and input into the pre-built target model for training. The image model can be a convolutional neural network model (CNN), and the sequence model can be a Transformer model. In this way, by using image data that can better reflect density information and sequence data that can better reflect information such as density parameters as input to the model, a more accurate target model can be trained.

[0070] Fig.6D and Fig. 6E A schematic diagram for optimizing the layout of a digital logic circuit according to an embodiment of the present application is shown.

[0071] like Fig.6DAs shown, there may be macro cells in the digital logic circuit whose positions need to be fixed. Therefore, in some embodiments, the computer device 100 can determine the target macro cells whose positions need to be fixed among the multiple second elements 602 of the current layout 100, for example, the first target macro cell 632 and the second target macro cell 634. Since there is a certain interval between the target macro cells, if the space in the interval area is utilized, the layout of the components can be further optimized. Therefore, in some embodiments, the computer device 100 can first determine the distance between the multiple target macro cells and the size of the standard cells in the multiple second elements 602 to determine the number of standard cells that can be placed according to the size of the blank area (for example, the target area 636) between the multiple target macro cells. Furthermore, the computer device 100 can adjust the target standard cells (for example, the first target standard cell 638 and the second target standard cell 640) that can be placed in the blank area among the multiple standard cells to the blank area (for example, the target area 636). Fig. 6E as shown) to further optimize the space utilization of digital logic circuits.

[0072] It should be noted that the method of this embodiment is not limited to using the congested components or density of digital logic circuits as optimization targets when extracting congested components or component density as layout features of cells. Optimizing the component layout of digital logic circuits will ultimately make the wiring line length shorter. Therefore, when the congested components or density are used as optimization targets, the line length is also used as optimization target.

[0073] The inventor of this application has found through experiments that, through the method of this application, the total line length of the digital logic circuit can be shortened by 2.6%, and the timing optimization result of the optimized digital logic circuit is 2.5%. It can be understood that the shortening of the line length means that the timing, power consumption and area of ​​the chip can be reduced. Therefore, the method of this application is of great help to improve the performance of the chip.

[0074] Figure 7 FIG. 7 is a flow chart of an exemplary method 700 for optimizing the layout of a digital logic circuit according to an embodiment of the present application. The method 700 may be performed as follows: Figure 1 The computer device 100 shown performs and may include the following steps.

[0075] In step 702, the layout diagram of the digital logic circuit is divided into a plurality of cells (eg, Fig. 6A , each cell including a plurality of elements (eg, Fig. 6A The second element 602 in FIG.

[0076] In some embodiments, the method further comprises: based on a netlist file (eg, Figure 5502) and layout files (e.g., Figure 5 ), determining design information of the digital logic circuit, the design information including at least one of area utilization, macro cell utilization or channel utilization; determining an initial density function value of the digital logic circuit based on the design information; dividing the layout diagram into a plurality of regions (for example, Figure 5 ) to obtain an initial layout of the digital logic circuit (eg, Figure 4 402 in the initial layout), the current layout includes the initial layout.

[0077] In some embodiments, the step of obtaining a target density function value according to a target model based on the layout characteristics of the cell further comprises: Figure 6B The method further comprises: determining the distance between the plurality of components based on the current layout 600 in the cell; determining the congested components in the cell based on the distance between the plurality of components; determining the congested components as the layout feature of the cell; and obtaining the target density function value according to the target model based on the layout feature of the cell. The target density function value can be used to adjust the position of the components to be optimized to avoid overlapping of the components.

[0078] In some embodiments, obtaining a target density function value according to a target model based on the layout characteristics of the cell further includes: determining a component density in the cell based on the current layout; determining the component density as a layout characteristic of the cell; and obtaining the target density function value according to the target model based on the layout characteristics of the cell. The target density function value can be used to adjust the position of the component to be optimized so that the denser components become dispersed.

[0079] In some embodiments, the obtaining of the target density function value according to the target model based on the layout characteristics of the cell further comprises: determining at least one of the density parameter or density function value of the element in the cell based on the current layout; determining the density parameter or density function value as the layout characteristics of the cell; and obtaining the target density function value according to the target model based on the layout characteristics of the cell. The placement positions of the elements in each cell will be gradually pushed out through the density function.

[0080] In some embodiments, the target model is trained by the following method: obtaining training data, the training data including image data and sequence data, the image data including at least one of the congestion component data or component density data of the cell, and the sequence data including at least one of the density parameter data or density function data of the cell; using the image data to train a pre-built image model and using the sequence data to train a pre-built sequence model to obtain the target model. In this way, using image data that can better reflect density information and sequence data that can better reflect information such as density parameters as inputs of the model can train a more accurate target model.

[0081] In some embodiments, obtaining a target density function value according to a target model based on the layout characteristics of the cell further comprises: iterating the target density function value multiple times at a certain frequency according to the target model based on the layout characteristics. Multiple iterative updates can obtain more accurate density parameters or density function values.

[0082] In step 704, based on the current layout of the digital logic circuit and an optimization target, the components to be optimized in the cell are determined, wherein the optimization target includes at least one of a line length target, a congestion target, or a density target.

[0083] In some embodiments, the determining the element to be optimized in the cell based on the current layout and the optimization target of the digital logic circuit further comprises: determining a plurality of target macro cells (e.g., Fig.6D The first target macrocell 632 and the second target macrocell 634 in the embodiment are determined as the components to be optimized. The macrocells whose positions need to be fixed are determined through this embodiment.

[0084] In some embodiments, adjusting the position of the element to be optimized in the cell based on the target density function value to optimize the layout of the digital logic circuit further includes: determining the distance between the plurality of target macro cells and the size of the plurality of standard cells in the plurality of elements; and positioning the target standard cells (e.g., Fig.6D The first target standard cell 638 and the second target standard cell 640 in the target macrocell are adjusted to the target area between the plurality of target macrocells (eg, Fig.6DThe adjustment includes at least one of swapping the position of the target standard cell or changing the position of the target standard cell. By adjusting the target standard cell that can be placed in the blank area among the plurality of standard cells to the blank area, the space utilization of the digital logic circuit can be further optimized.

[0085] In step 706, a target density function value is obtained according to a target model based on the layout characteristics of the cells.

[0086] In step 708, based on the target density function value, the position of the element to be optimized in the cell is adjusted to optimize the layout of the digital logic circuit.

[0087] The present application provides a method, device and storage medium for optimizing the layout of a digital logic circuit. The method divides the layout diagram of the digital logic circuit into multiple cells, each cell includes multiple components, and determines the components to be optimized in the cell based on the current layout and optimization target of the digital logic circuit. The optimization target includes at least one of the line length target, the congestion target or the density target. Based on the layout characteristics of the cell, the target density function value is obtained according to the target model. Based on the target density function value, the position of the component to be optimized in the cell is adjusted to optimize the layout of the digital logic circuit. Through the method of the present application, automatic layout optimization of digital logic circuits can be achieved, saving labor time and cost, and further improving the performance of the chip. At the same time, corresponding layout features can be extracted for different optimization targets, so as to obtain more targeted density function values ​​for optimizing component layout.

[0088] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0089] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0090] Based on the same technical concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute method 700 described in any of the above embodiments.

[0091] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0092] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 700 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0093] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0094] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device may be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0095] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0096] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A method for optimizing the layout of a digital logic circuit, characterized in that: The method comprises: Dividing the layout diagram of the digital logic circuit into a plurality of cells, each cell including a plurality of components; Determining a component to be optimized in the cell based on a current layout of the digital logic circuit and an optimization target, the optimization target comprising at least one of a line length target, a congestion target, or a density target; Based on the layout characteristics of the cells, obtaining a target density function value according to a target model; and Based on the target density function value, the position of the element to be optimized in the cell is adjusted to optimize the layout of the digital logic circuit.

2. The method according to claim 1, characterized in that The step of obtaining a target density function value based on the layout characteristics of the cell according to the target model further includes: Based on the current layout, determining distances between the plurality of components; determining a congested element in the cell based on distances between the plurality of elements; determining the congested element as a layout feature of the cell; Based on the layout characteristics of the cells, the target density function value is obtained according to the target model.

3. The method according to claim 1, characterized in that The step of obtaining a target density function value based on the layout characteristics of the cell according to the target model further includes: Based on the current layout, determining a density of components in the cell; determining the component density as a layout feature of the cell; Based on the layout characteristics of the cells, the target density function value is obtained according to the target model.

4. The method according to claim 1, characterized in that The step of obtaining a target density function value based on the layout characteristics of the cell according to the target model further includes: Based on the current layout, determining at least one of a density parameter or a density function value of the components in the cell; Determining the density parameter or density function value as a layout feature of the cell; Based on the layout characteristics of the cells, the target density function value is obtained according to the target model.

5. The method according to claim 1, characterized in that The target model is trained by the following method: Acquire training data, the training data comprising image data and sequence data, the image data comprising at least one of congestion component data or component density data of the cell, the sequence data comprising at least one of density parameter data or density function data of the cell; The pre-built image model is trained using the picture data and the pre-built sequence model is trained using the sequence data to obtain the target model.

6. The method according to claim 1, characterized in that The step of determining the element to be optimized in the cell based on the current layout and optimization target of the digital logic circuit further comprises: Based on the current layout and the optimization target, determining a plurality of target macro cells among the plurality of components; The plurality of target macro cells are determined as the elements to be optimized.

7. The method according to claim 6, characterized in that The adjusting the position of the element to be optimized in the cell based on the target density function value to optimize the layout of the digital logic circuit further includes: determining distances between the plurality of target macro cells and sizes of a plurality of standard cells in the plurality of components; Based on the distances between the multiple target macro cells and the sizes of the multiple standard cells, a target standard cell among the multiple standard cells is adjusted to a target region between the multiple target macro cells, wherein the adjustment includes at least one of swapping positions of the target standard cells or changing positions of the target standard cells.

8. The method according to claim 1, characterized in that The method further comprises: Determining design information of the digital logic circuit based on a netlist file and a layout file of the digital logic circuit, the design information comprising at least one of an area utilization rate, a macro cell utilization rate, or a channel utilization rate; determining an initial density function value of the digital logic circuit based on the design information; The layout diagram is divided into a plurality of regions based on the initial density function value to obtain an initial layout of the digital logic circuit, wherein the current layout includes the initial layout.

9. The method according to claim 1, characterized in that The step of obtaining a target density function value based on the layout characteristics of the cell according to the target model further includes: Based on the layout features, the target density function value is iterated multiple times at a certain frequency according to the target model.

10. A computer device comprising: One or more processors, memory; as well as one or more programs; It is characterized in that the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1-9.

11. A non-volatile computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 9.

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