Lead mfg. method and method for shortening distance between lead an pattern

Abstract

The method for reducing space between wires includes steps: providing substrate; forming first conductor layer on substrate; patternizing first conductor layer to form openings on the first conductor layer; forming gap walls on sidewall of the first conductor layer, and widths of these gap walls are smaller than widths of openings; on substrate, forming second conductor layer to be filled to the openings, and to expose top of each gap wall. Gap wall separates first conductor layer from second conductor layer. Width of gap wall is equal to space between first conductor layer and second conductor layer.

Description

technical field [0001] The invention relates to a semiconductor process, in particular to a method for manufacturing a wire on the semiconductor process and a method for reducing the distance between the wire and a pattern. Background technique [0002] Today, with the vigorous development of integrated circuits, the miniaturization and integration of components is an inevitable trend, and it is also an important topic for active development in the industry. The most important factor affecting the size of components in the entire semiconductor process lies in the technology of photolithography (Photolithography) process . [0003] In terms of the current semiconductor process technology, in order to further improve the resolution of the photolithography process, the machines, photomasks and even light sources used may be expensive. Moreover, under the condition that the accumulation degree of each component layout is increasing day by day, the overlay accuracy (Overlay Accu...

AI Technical Summary

Problems solved by technology

However, due to limitations in photolithography technology, the pattern of the polysilicon layer 110 may deviate due to overlay errors generated during the patterning of the photoresist layer, as shown by the dotted line in FIG. 1B shows that it cannot be accurately formed between two shallow trench isolations 101

This kind of error will cause abnormal electrical connection between word lines, or between word lines and components, which will lead to a significant decrease in the overall performance and reliability of semiconductor components, and may even cause the components to fail to operate.

Images