Reducing the fetch time of target instructions of a predicted taken branch instruction

a branch instruction and target instruction technology, applied in the field of computers, can solve the problems of further dead-time in the pipeline, and achieve the effect of reducing the fetch time of target instructions of a predicted taken branch instruction

Inactive Publication Date: 2008-11-06
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach eliminates the two-cycle delay, enabling more instructions to be processed in a given period by allowing target instructions to be decoded and enqueued in the same clock cycle as the branch instruction, thus improving pipeline efficiency.

Problems solved by technology

This delay results in dead-time in the pipeline where no instructions are executed as illustrated in FIG. 1.
This may result in further dead-time in the pipeline than illustrated in FIG. 1.

Method used

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  • Reducing the fetch time of target instructions of a predicted taken branch instruction
  • Reducing the fetch time of target instructions of a predicted taken branch instruction
  • Reducing the fetch time of target instructions of a predicted taken branch instruction

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Embodiment Construction

[0025]The present invention comprises a method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. In one embodiment of the present invention, each entry in a buffer, referred to herein as a “branch target buffer” (BTB), may store an address of a branch instruction predicted taken, the instructions beginning at the target address of the branch instruction predicted taken, branch prediction information and the next fetch address. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match and a branch in the fetch group is predicted taken, then the instruction fetched from the instruction cache is considered to have a BTB hit. Further, if there is a BTB hit, the ins...

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Abstract

A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

Description

TECHNICAL FIELD[0001]The present invention relates to the field of instruction execution in computers, and more particularly to reducing the fetch time of target instructions of a predicted taken branch instruction.BACKGROUND INFORMATION[0002]Program instructions for a microprocessor are typically stored in sequential, addressable locations within a memory. When these instructions are processed, the instructions may be fetched from consecutive memory locations and stored in a cache commonly referred to as an instruction cache. The instructions may later be retrieved from the instruction cache and executed. Each time an instruction is fetched from memory, a next instruction pointer within the microprocessor may be updated so that it contains the address of the next instruction in the sequence. The next instruction in the sequence may commonly be referred to as the next sequential instruction pointer. Sequential instruction fetching, updating of the next instruction pointer and execut...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G06F9/312
CPCG06F9/3804G06F9/3844
InventorDOING, RICHARD WILLIAMOLSSON, BRETTTSUCHIYA, KENICHI
OwnerINT BUSINESS MASCH CORP