Semiconductor integrated circuit device and test method therefor
a technology of integrated circuit and test method, which is applied in the direction of electronic circuit testing, measurement devices, instruments, etc., can solve the problems of reducing the tolerance of the system against increasing the operational speed or reducing the power supply voltage, and increasing the area of the bisi circui
Inactive Publication Date: 2010-10-14
NEC CORP
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[0029]A method for testing a semiconductor integrated circuit device according to an eighth modification may further include: applying disturbance to the circuit under test only during the period of processing the preset input signal; and increasing or decreasing the strength of the disturbance each time the disturbance is applied.
[0031]The present invention provides the following advantage, but not restricted thereto. In the semiconductor integrated circuit device according to the present invention, it is possible to measure disturbance tolerance of a circuit under test provided in a semiconductor integrated circuit device without halting the operation of the circuit under test in case the operation frequency of the input / output circuit of the semiconductor integrated circuit device or a tester is lower than the frequency of the test input signal.
Problems solved by technology
Hence, there is raised a problem that the area of the BISI circuit is increased.
In addition, such a problem may be presented in which it is difficult to predict an ideal output signal corresponding to the test input signal.
By the latent microdefects are meant those faults which are not obstructive to the system operation under a rated condition but which lower the tolerance of the system against increasing the operational speed or against decreasing the power supply voltage.
That is, the latent microdefects tend to give rise to a lowered operational speed or to an abnormal increase in power, depending upon an environment in a destination of shipment, thus possibly leading to deterioration with lapse of time.
To detect the latent microdefects, it is not sufficient to test the semiconductor integrated circuit device as to whether or not the device may be in operation under rated conditions.
However, if the BIST is used, as in the method described in Patent Document 2, there is presented a problem that, since a larger number of different sorts of data are generated in the inside of the BIST, a larger proportion of the area of the BIST is taken up for generating the data.
Therefore, it is difficult to realize a means for predicting an ideal output signal matched to the BISI input signal.
However, the former way of testing suffers from a problem that the margin that allows for a test is restricted, while the latter way of testing suffers from a problem that the measurement time is prolonged.
However, in the former case, the range of the delay margin that can be checked is restricted, whereas, in the latter case, the measurement time is protracted.
Therefore, there is a problem that test time is protracted owing to the limit on the operation frequency of the input / output circuit of the semiconductor integrated circuit device 160 or the frequency of the signal that can be received by the tester 200.
However, if the operation frequency of the external tester 200 is slower than the operation frequency of the circuit under test 150, there is raised a problem that the test time is protracted.
Therefore, there is a problem that test time is protracted by the limit on the operation frequency of the input / output circuit of the semiconductor integrated circuit device 160 or on the signal frequency that may be received by the tester 200.
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[0055]An example of the semiconductor integrated circuit device according to an example will now be described in detail with reference to the drawings.
[0056]FIG. 1 is a block diagram showing an arrangement of a semiconductor integrated circuit device of the present example.
[0057]Referring to FIG. 1, the semiconductor integrated circuit device 60 includes the input signal counter 40 that counts in a range between 0 and N-1, from one clock cycle to another, and the input signal storage unit 10. The input signal storage unit holds an N-number of input signals and selects one of the signals in response to the count of the input signal counter 40 (input signal count) to output the signal selected. The semiconductor integrated circuit device also includes the input signal disturbance unit 30 and the normal output signal counter 20. The input signal disturbance unit 30 generates the disturbance only when the input signal count is K, where K is an integer from 0 to N-1, and increases the di...
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A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit under test repeats processing on each of one or more input signals of an input signal set sequentially, a plural number of times.
Description
[0001]The present application is the National Phase of PCT / JP2008 / 071230, filed on Nov. 21, 2008, which claims priority rights based on the Japanese Patent Application 2007-301127, filed in Japan on Nov. 21, 2007, the disclosure of which is to be incorporated in its entirety herein by reference.TECHNICAL FIELD[0002]This invention relates to a semiconductor integrated circuit device and a test method therefor.BACKGROUND ART[0003]A semiconductor integrated circuit device is tested, before its shipment, as to whether or not its internal logic circuit or memory circuit may be in normal operation. FIG. 4 depicts a block diagram showing a conventional semiconductor integrated circuit device 160. Referring to FIG. 4, in a conventional test method, after a test input signal is applied from an external tester 200 to the inside of the semiconductor integrated circuit device 160 and a clock signal is generated, a comparison circuit 120 determines whether or not the output signal of a device un...
Claims
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CPCG01R31/319G01R31/31725
InventorNOSE, KOICHIMIZUNO, MASAYUKI
OwnerNEC CORP