Spacer and process to enhance the strain in the channel with stress liner
a stress liner and channel technology, applied in the space field, can solve the problems of oxide spacers of 10-20 nm remaining, moderate device performance benefit, and high cost, and achieve the effect of enhancing the strain in the channel
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
first embodiment
[0022]the invention, illustrated in FIGS. 1-9, enhances strain in the channel with a stress liner. As shown in FIG. 1, a gate 10, e.g., a poly gate, is formed on a substrate 20, e.g., silicon or other suitable material, through a poly gate etch. An insulating layer 15 is formed between gate 10 and substrate 20. In FIG. 2, an oxide layer 30 is formed over gate 10 and substrate 20 to protect gate 10. Preferably, oxide layer 30 has a thickness that generally corresponds to the thickness of insulating layer 15 between gate 10 and substrate 20. Oxide layer 30, e.g., 1-5 nm, can be formed by gate reoxidation. It is noted that, in the prior art, oxide layers protecting the gate have a thickness of 10-20 nm. Subsequently, a nitride layer 40, e.g., 10-15 nm, is deposited over the oxide layer by nitride deposition in FIG. 3. In FIG. 4, portions of the nitride and oxide layers are etched, e.g., via reactive ion etching (RIB) to form first spacers 50 on the sides of gate 10. In this regard, the...
second embodiment
[0026]In the invention, the formation process in accordance with FIGS. 1-6 is performed. Subsequently, as shown in FIG. 10, a deep source / drain implant is performed. However, in contrast to the previous embodiment, silicide formation does not yet occur. In FIG. 11, a nitride / oxide / nitride removal, e.g., via wet etch or RIE, is performed. Thus, as shown in FIG. 11, an L-shaped spacer 30′ is formed at the edges of gate 10. FIG. 12 shows a silicide formation 90 on gate 10 and the source / drain region. Thereafter, the process proceeds in accordance with FIG. 9, such that a stress liner 100, e.g., a nitride CA (contact) liner, is deposited over gate 10, L-shaped spacer 30′, and substrate 20, whereby stain in the channel is enhanced due to the thin construction of L-shaped spacer 30′ separating gate 10 and stress liner 100.
[0027]The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and s...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More