Interconnection structure of semiconductor device

a technology of interconnection structure and semiconductor device, which is applied in the details of semiconductor/solid-state devices, semiconductor devices, electrical appliances, etc., can solve the problems of deteriorating the reliability of semiconductor devices, voids occurring, and insufficient structure of semiconductor devices to prevent voids

Inactive Publication Date: 2009-02-10
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively reduces voids in the main interconnection body by promoting their formation in the dummy interconnection, enhancing the reliability and durability of semiconductor devices by managing stress migration and concentration.

Problems solved by technology

In an interconnection structure of a semiconductor device, there is a possibility that a void occurs in an interconnection such as a via or the bottom of a via due to stress migration.
Further, the void may cause a disconnection in the interconnection, deteriorating the reliability of the semiconductor device.
However, this structure of the semiconductor device is insufficient to prevent a void from occurring locally such as at the bottom of a via.
Furthermore, in the interconnection within an interconnection layer, since the compressive stress and the tensile stress act on the interconnection, stress concentrates at a weak portion within the interconnection such as a crystal grain boundary or the like, reducing bonding strength in the crystal grain boundary or the like.
However, although this structure is effective for stress relief of an interconnection layer as a whole, its effect is insufficient for local stress, because the dummy region is far from the interconnection for which stress should be relieved.
Further, since the dummy region is formed within the interconnection layer, it is insufficient to relieve local stress generated at such as the bottom of a via.
Furthermore, when a portion between the interconnection and the dummy region is formed of a material such as a low-k material having weak mechanical strength, the dummy region provides the effect of the stress relief to a narrower range, further reducing the effect.

Method used

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  • Interconnection structure of semiconductor device
  • Interconnection structure of semiconductor device
  • Interconnection structure of semiconductor device

Examples

Experimental program
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first embodiment

[0022]Referring to FIGS. 1 to 8, a first embodiment will be described.

[0023]Referring to FIGS. 1 and 2, an interconnection structure of a semiconductor device will be described. In the interconnection structure of the present embodiment, an interconnection is provided with a dummy interconnection 15 connected to an interconnection body 11. The whole of dummy interconnection 15 serves as a stress concentration portion 21 in which tensile stress higher than that of interconnection body 11 is generated.

[0024]Interconnection body 11 is an interconnection required for constituting a circuit in the semiconductor device, and is made of Cu. FIG. 1 illustrates a lower interconnection 11A, an upper interconnection 11C, and a via 11B connecting lower interconnection 11A and upper interconnection 11C, as interconnection body 11.

[0025]Dummy interconnection 15 is an interconnection unnecessary for constituting a circuit in the semiconductor device, and is a portion in which even the occurrence of...

second embodiment

[0043]In the following, a second embodiment will be described with reference to FIGS. 9 to 14.

[0044]Referring to FIG. 9, an interconnection structure of a semiconductor device will be described. It is to be noted that a structure corresponding to that in the first embodiment will be identified by a reference number identical to that in the first embodiment, and description thereof will not be repeated here. In the interconnection structure of the present embodiment, an interconnection is provided with an interconnection laterally extending from interconnection body 11, as dummy interconnection 15 connected to interconnection body 11. Substantially the whole of dummy interconnection 15 serves as stress concentration portion 21 in which tensile stress higher than that of interconnection body 11 acts.

[0045]In the present embodiment, dummy interconnection 15 is provided in the same layer as interconnection body 11. Although interconnection body 11 and dummy interconnection 15 are made o...

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Abstract

An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Description

RELATED APPLICATIONS[0001]This application is a continuation of application Ser. No. 10 / 725,384, filed on Dec. 3, 2003 now U.S. Pat. No. 7,154,184, which in turn claims the benefit of Japanese Patent Application No. 2003-165013, filed on Jun. 10, 2003, the disclosures of which Applications are incorporated by reference herein.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to an interconnection structure of a semiconductor device having an interconnection provided with a stress concentration portion.[0004]2. Description of the Background Art[0005]In an interconnection structure of a semiconductor device, there is a possibility that a void occurs in an interconnection such as a via or the bottom of a via due to stress migration. Further, the void may cause a disconnection in the interconnection, deteriorating the reliability of the semiconductor device.[0006]To prevent the occurrence of a void, for example, in semiconductor devices descri...

Claims

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Application Information

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Patent Type & AuthorityPatents(United States)
IPC IPC(8): H01L23/48H01L21/3205H01L21/28H01L21/768H01L23/52H01L23/522H01L23/532
CPCH01L21/768H01L23/5226H01L23/522H01L23/53228H01L2924/0002H01L2924/00H01L21/28
InventorASAI, KOYUTOBIMATSU, HIROSHIKAWATA, HIROYUKISAWADA, MAHITO
OwnerRENESAS ELECTRONICS CORP