Nonvolatile semiconductor memory device
a non-volatile, semiconductor technology, applied in semiconductor devices, electrical devices, instruments, etc., can solve the problem of power consumption also being required to be kept low
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first embodiment
[0040][First Embodiment]
[0041]First, an overall configuration of a nonvolatile semiconductor memory device in accordance with a first embodiment is described with reference to FIG. 1. FIG. 1 is a circuit diagram of the nonvolatile semiconductor memory device in accordance with the first embodiment.
[0042]As shown in FIG. 1, the nonvolatile semiconductor memory device in accordance with the first embodiment includes a memory cell array AR1 and a control circuit AR2 provided at a periphery of the memory cell array AR1.
[0043]As shown in FIG. 1, the memory cell array AR1 is configured having a plurality of memory strings MS arranged therein, each of the memory strings MS having electrically rewritable memory transistors MTr1-MTr8 (memory cells) connected in series. The control circuit AR2 is configured by various kinds of control circuits configured to control a voltage applied to a gate and so on of the memory transistors MTr (MTr1-MTr8). The control circuit AR2 executes a write operati...
second embodiment
[0149][Second Embodiment]
[0150]Next, a nonvolatile semiconductor memory device in accordance with a second embodiment is described with reference to FIG. 29. FIG. 29 is a perspective view showing a stacking structure of the nonvolatile semiconductor memory device in accordance with the second embodiment. Note that in the second embodiment, identical symbols are assigned to configurations similar to those in the first embodiment and descriptions thereof are omitted.
[0151]Now, in the first embodiment, the memory semiconductor layer 34 is formed in a U shape extending in the stacking direction as viewed from the row direction. In contrast, as shown in FIG. 29, a memory semiconductor layer 34A in accordance with the second embodiment is formed in an I shape (column shape) as viewed from the row direction and the column direction. Word line conductive layers 31Aa-31Ad are formed in a plate shape extending in the row direction and column direction on a memory block MB basis, and are forme...
third embodiment
[0156][Third Embodiment]
[0157]Next, a nonvolatile semiconductor memory device in accordance with a third embodiment is described with reference to FIG. 30. FIG. 30 is a perspective view showing a stacking structure of the nonvolatile semiconductor memory device in accordance with the third embodiment. Note that in the third embodiment, identical symbols are assigned to configurations similar to those in the first and second embodiments and descriptions thereof are omitted.
[0158]As shown in FIG. 30, in the third embodiment, a second source side conductive layer 45Ba is formed in a rectangular plate shape surrounding a plurality of second source side columnar semiconductor layers 48Aa aligned in the row direction and the column direction on a memory block MB basis. Moreover, a second drain side conductive layer 45Bb is formed in a rectangular plate shape surrounding a plurality of second drain side columnar semiconductor layers 48Ab aligned in the row direction and the column directio...
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