Double-selectable conduction type double-bracket gate-controlled source-drain resistance variable transistor and manufacturing method thereof
A conductivity type and transistor technology, which is applied in semiconductor/solid-state device manufacturing, transistors, semiconductor devices, etc., can solve the problems of inability to change conductivity type, non-switchable conductivity type, and reduced control ability of gate electrode to drain region and source region, etc.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2020-03-03
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Abstract
Description
technical field
[0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, in particular to a double-bracket gate-controlled source-drain resistance variable transistor with double-selection conduction type and a manufacturing method suitable for low-power integrated circuit manufacturing. Background technique
[0002] When ordinary tunneling field effect transistors are used as switching devices, the tunneling mechanism of carriers is used, which can make the subthreshold swing of ordinary tunneling field effect transistors better than the 60mV / dec limit of MOSFETs type devices. However, tunneling field effect transistors based on silicon-based materials have limited tunneling probability due to the limited band gap. Compared with MOSFETs, it is difficult to generate a conduction current of the same order. More seriously, the source and drain electrodes Doping with impurities of different conductivity types, the asymmetric structural ch...
Examples
Embodiment Construction
[0061] Below in conjunction with accompanying drawing, the present invention will be further described:
[0062] Such as figure 1 , figure 2 , image 3 and Figure 4 As shown, the dual-selection conduction type double-bracket gate-controlled source-drain resistance variable transistor includes a silicon substrate 12 of an SOI wafer, and above the silicon substrate 12 of the SOI wafer is a substrate insulating layer 11 of the SOI wafer. Above the round insulating substrate layer 11 are monocrystalline silicon thin film 1, part of folded auxiliary gate 2, source-drain interchangeable intrinsic region a3, source-drain interchangeable intrinsic region b4, metal source-drain interchangeable interchangeable region a5, metal source-drain interchangeable region b6, part of the gate electrode insulating layer 7, double-bracket gate electrode 8 and part of the insulating dielectric barrier layer 13; the single crystal silicon thin film 1 has an impurity concentration lower than 10 ...