A lead frame-free semiconductor packaging structure and preparation method thereof

Abstract

The present invention discloses a semiconductor packaging structure without a lead frame and a preparation method thereof, the structure comprising: a metal substrate, which is divided into at least one independent segmented area, the segmented area comprising two external connection pin areas and at least one chip bonding area; at least one chip, which is respectively arranged on the upper surface of the chip bonding area, the chip and the external connection pin area are interconnected by bonding wires; packaging material, which packages the metal substrate, the chip and the bonding wire. In the entire packaging process and the material list of the present invention, there is no lead frame required for traditional packaging, and the chip bonding area and the external connection pin area are grown on a thin copper sheet, thereby achieving a smaller volume and a higher device density, and the preparation process also has higher efficiency and lower cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor packaging structure without a lead frame and a preparation method thereof. Background Art

[0002] In the semiconductor packaging process, lead frames are usually used as chip carriers. Lead frames are key structural components that use bonding materials to achieve electrical connection between the internal circuit leads of the chip and the external leads to form an electrical circuit. They serve as a bridge to connect to external wires. Lead frames are required in most semiconductor integrated blocks and are important basic materials in the electronic information industry.

[0003] However, with the development of increasing semiconductor integration and reducing the size of terminal electronic products, the semiconductor packaging structure based on the lead frame also has limitations. In particular, when used in the control system of the motor, since some of its applications do not require much power and the size of the motor is relatively small, this also requires the motor control system to have a smaller size and a higher functional density. However, due to the limitation of the lead frame of the device package, it is impossible to make very complex interconnections, and it is impossible to integrate chips with various functions into a smaller package, which cannot meet the use requirements. Therefore, it is necessary to improve the existing semiconductor packaging structure based on the lead frame and the corresponding preparation method so that the semiconductor packaging structure can have a smaller volume and a higher device density. Summary of the invention

[0004] The embodiment of the present invention provides a semiconductor packaging structure without a lead frame and a preparation method thereof, so as to solve the problem that the semiconductor packaging structure based on the lead frame in the prior art cannot achieve a smaller volume and a higher device density and cannot meet the use requirements.

[0005] In a first aspect, an embodiment of the present invention provides a lead frame-less semiconductor packaging structure, comprising:

[0006] A metal substrate, which is divided into at least one divided area independent of each other, wherein the divided area includes two external connection pin areas and at least one chip bonding area;

[0007] At least one chip, which is respectively arranged on the upper surface of the chip bonding area, the chip bonding area at least covers the area corresponding to the chip, and the chip and the external connection pin area are interconnected through bonding wires;

[0008] The packaging material packages the metal substrate, the chip and the bonding wires, and exposes the packaging material to the outside of at least one side of the two external connection pin regions facing outwards.

[0009] As a preferred embodiment of the first aspect of the present invention, the segmentation region further includes at least one interconnection circuit area, and the chip, the external connection pin area and the interconnection circuit area are interconnected through the bonding wires.

[0010] As a preferred embodiment of the first aspect of the present invention, a chip bonding material is further provided between the upper surface of the chip bonding area and the chip.

[0011] As a preferred embodiment of the first aspect of the present invention, the chip bonding material is at least one of conductive glue, silver paste or solder paste.

[0012] As a preferred embodiment of the first aspect of the present invention, the metal substrate comprises a gold electroplating layer and a copper electroplating layer, wherein the copper electroplating layer is located above the gold electroplating layer.

[0013] As a preferred embodiment of the first aspect of the present invention, the thickness of the gold electroplating layer is 0.9-1.1 μm, and the thickness of the copper electroplating layer is 100-200 μm.

[0014] As a preferred embodiment of the first aspect of the present invention, the chip includes a control chip, a power MOSFET chip and a driver chip.

[0015] In a second aspect, an embodiment of the present invention provides a method for preparing a lead frame-less semiconductor packaging structure, comprising:

[0016] Performing electroplating operation on the segmented area on the upper surface of the copper sheet substrate to form a metal substrate including a gold electroplating layer and a copper electroplating layer, wherein the segmented area includes two external connection pin areas and at least one chip bonding area;

[0017] Disposing at least one chip on the upper surface of the chip bonding area through a chip bonding material, the chip bonding area at least covers the area corresponding to the chip, and interconnecting the chip and the external connection pin area through bonding wires;

[0018] Encapsulating the metal substrate, the chip and the bonding wires with an encapsulation material, and exposing the encapsulation material to at least one side of the two external connection pin regions facing outwards;

[0019] The copper substrate is removed by etching.

[0020] As a preferred embodiment of the second aspect of the present invention, the segmentation region further includes at least one interconnection line region, and the chip, the external connection pin region and the interconnection line region are interconnected through the bonding wires.

[0021] As a preferred embodiment of the second aspect of the present invention, the electroplating operation is performed on the segmented areas on the upper surface of the copper sheet substrate to form a metal substrate including a gold electroplating layer and a copper electroplating layer, comprising:

[0022] Coating a photoresist on the upper surface of the copper substrate to form a photoresist layer;

[0023] Removing the portion of the photoresist layer located above the segmentation area by a development process to form at least one photoresist window area;

[0024] Performing gold electroplating and copper electroplating in sequence in the photoresist window area to form a metal substrate including a gold electroplating layer and a copper electroplating layer;

[0025] The remaining portion on the photoresist layer is removed.

[0026] The lead frame-free semiconductor packaging structure and the preparation method thereof provided in the embodiments of the present invention improve upon the existing lead frame-based semiconductor packaging structure and the corresponding preparation method thereof. In the entire packaging process and the bill of materials, there is no lead frame required for traditional packaging. Instead, a chip bonding area and an external connection pin area are grown on a thin copper sheet, thereby achieving a smaller volume and higher device density than a traditional lead frame-based semiconductor packaging structure, and the preparation process also has higher efficiency and lower cost.

[0027] At the same time, compared with the traditional semiconductor packaging structure in which each chip is separate and needs to be further integrated, it has the characteristics of high integration, easy use and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic structural diagram of a lead frame-less semiconductor packaging structure provided by an embodiment of the present invention;

[0030] Figure 2 A schematic flow chart of a method for preparing a lead frame-free semiconductor packaging structure provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram of a copper sheet substrate provided in an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a photoresist layer formed on the upper surface of a copper substrate according to an embodiment of the present invention;

[0033] Figure 5A schematic diagram of a photoresist window area formed on a photoresist layer according to an embodiment of the present invention;

[0034] Figure 6 A schematic diagram of a process of forming a gold electroplating layer in a photoresist window region according to an embodiment of the present invention;

[0035] Figure 7 A schematic diagram of a copper electroplating layer formed in a photoresist window area according to an embodiment of the present invention;

[0036] Figure 8 A schematic diagram of removing the remaining portion of the photoresist layer provided by an embodiment of the present invention;

[0037] Fig. 9 A schematic diagram of a chip bonding material printed on the upper surface of the chip bonding area provided in an embodiment of the present invention;

[0038] Fig.10 A schematic diagram of a chip being arranged on the upper surface of a chip bonding area according to an embodiment of the present invention;

[0039] Fig.11 A schematic diagram of a chip, an external connection pin area and an interconnection line area interconnected by bonding wires provided in an embodiment of the present invention;

[0040] Fig.12 A schematic diagram of a metal substrate, a chip and bonding wires encapsulated by an encapsulation material provided in an embodiment of the present invention;

[0041] Fig.13 A schematic diagram of an embodiment of the present invention after the copper substrate is removed;

[0042] Fig.14 A schematic diagram of cutting a packaging material into independent products according to an embodiment of the present invention.

[0043] Among them, 100, metal substrate, 101, gold electroplating layer, 102, copper electroplating layer, 100-1, external connection pin area, 100-2, chip bonding area, 100-3, interconnection line area, 200, chip bonding material, 300, bonding wire, 400, control chip, 500, power MOSFET chip, 600, driver chip, 700, packaging material, 800, copper substrate, 900, photoresist layer, 901, photoresist window area. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0045] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0046] As an actuator, the motor plays a very important role in human life and production as an extension of human hands and feet. Different types of motors need to be controlled accordingly in order to operate at different speeds and torques. Generally, the main components required for motor control systems are control chips, power MOSFET chips, and driver chips.

[0047] In practical applications, some applications do not require much power, and the size of the motor is relatively small, which correspondingly requires the motor control system to have a smaller size and greater functional density. However, due to the limitation of the lead frame of the package, it is impossible to make very complex interconnections, and it is also impossible to integrate chips with various functions into one package. Therefore, it is necessary to propose a lead frame-free package and preparation process for the motor control system to meet the use requirements.

[0048] The embodiment of the present invention discloses a semiconductor packaging structure without a lead frame, referring to Figure 1 As shown, the structure mainly includes:

[0049] A metal substrate 100 is divided into at least one divided area independent of each other, and the divided area includes two external connection pin areas 100 - 1 and at least one chip bonding area 100 - 2;

[0050] At least one chip is disposed on the upper surface of the chip bonding area 100 - 2 , the chip bonding area 100 - 2 at least covers the area corresponding to the chip, and the chip and the external connection pin area 100 - 1 are interconnected through bonding wires 300 ;

[0051] The packaging material 700 packages the metal substrate 100 , the chip and the bonding wires 300 , and exposes the packaging material 700 on at least one side of the two external connection pin regions 100 - 1 facing outward.

[0052] In this embodiment, according to actual setting requirements, the metal substrate is divided into a plurality of independent division areas, and the division areas need to include at least two external connection pin areas and a plurality of chip bonding areas. Among them, the two external connection pin areas are used to connect with external devices, and the chip bonding areas are used to bond each chip.

[0053] After each chip is bonded to its corresponding chip bonding area, each chip is then interconnected with the external connection pin area and the interconnection line area through bonding wires. Finally, the metal substrate, chip and bonding wire are packaged with packaging materials, and the packaging materials need to be exposed on the opposite side of the two external connection pin areas.

[0054] In the above structure, there is no lead frame required for traditional packaging. Instead, the chip bonding area and external connection pin area are grown on a thin copper sheet, thereby achieving a smaller volume and higher device density than the traditional lead frame-based semiconductor packaging structure. The preparation process also has higher efficiency and lower cost.

[0055] At the same time, compared with the traditional semiconductor packaging structure in which each chip is separate and needs to be further integrated, it has the characteristics of high integration, easy use and high reliability.

[0056] Preferably, the segmentation region further includes at least one interconnection line area 100 - 3 , and the chip, the external connection pin area 100 - 1 and the interconnection line area 100 - 3 are interconnected through bonding wires 300 .

[0057] Specifically, the interconnection line area is used to replace a portion of bonding wires that have a large span or may cross wires, and it can also replace bonding wires to pass larger currents. Therefore, in general, if the interconnection relationship between each chip and the external connection pin area can be completed only by bonding wires and the overcurrent capacity can be achieved, there is no need to set up an interconnection line area separately.

[0058] Similarly, the number and position of the interconnection line area also depend on the specific situation, and those skilled in the art can set them according to the actual situation, which will not be described in detail here. In this embodiment, an interconnection line area is set between two chip bonding areas.

[0059] Preferably, the metal substrate 100 includes a gold electroplating layer 101 and a copper electroplating layer 102 , wherein the copper electroplating layer 102 is located above the gold electroplating layer 101 .

[0060] Specifically, the chip bonding area, the interconnection line area and the external connection pin area are located on the upper surface of the metal substrate. After the chip bonding area, the interconnection line area and the external connection pin area are grown on the thin copper sheet formed by the copper electroplating layer, a thin gold sheet formed by the gold electroplating layer is also arranged under the thin copper sheet.

[0061] During the preparation of the packaging structure, when it is necessary to etch away the copper substrate under the metal substrate, the gold electroplating layer can protect the copper electroplating layer in the chip bonding area, interconnection line area and external pin area from corrosion. At the same time, the gold electroplating layer can also serve as an anti-oxidation layer for the finished chip pins.

[0062] Preferably, the thickness of the gold electroplating layer is 0.9-1.1 μm, and the thickness of the copper electroplating layer is 100-200 μm.

[0063] Specifically, according to actual use requirements, the gold electroplating layer does not need to be too thick, and setting its thickness to 0.9 to 1.1 μm can meet the use requirements, while the thickness of the copper electroplating layer needs to be set to 100 to 200 μm to meet the use requirements.

[0064] Preferably, a chip bonding material 200 is further disposed between the upper surface of the chip bonding area 100 - 2 and the chip.

[0065] Specifically, before packaging the product, a plurality of chips are bonded to the upper surfaces of the corresponding chip bonding areas using a chip bonding material.

[0066] Preferably, the chip bonding material 200 is at least one of conductive glue, silver paste or solder paste.

[0067] Specifically, the chip bonding materials are preferably the following materials, which can achieve better bonding effects.

[0068] Preferably, the chip includes a control chip 400 , a power MOSFET chip 500 and a driver chip 600 .

[0069] Specifically, when it is applied in the motor control system, the number of driver chips and power MOSFET chips used will vary according to different motor drive products, but the relative connection relationship and structure are the same. For example, a brushed DC motor uses 2 driver chips and 4 power MOSFET chips, while a three-phase brushless DC motor uses 3 driver chips and 6 power MOSFET chips.

[0070] This embodiment does not limit the specific number of each type of chip selected. At the same time, the type of chip can also be selected by technical personnel in this field according to different application scenarios and requirements. The embodiment of the present invention is only described by taking the application in the motor control system as an example.

[0071] Likewise, the number and size of the chip bonding areas corresponding to the chips correspond to the number and size of the chips provided.

[0072] Preferably, the bonding wire 300 is made of gold or copper metal material.

[0073] Specifically, the bonding wire is made of gold or copper metal material. Generally, when used as interconnection wires between signals, it is better to use gold wires; and when used as interconnection wires between larger current paths, it is better to use copper wires.

[0074] In order to more clearly introduce the semiconductor package structure without a lead frame provided by the embodiment of the present invention, the semiconductor package structure without a lead frame provided by the embodiment of the present invention is introduced in more detail below in combination with the preparation method of the semiconductor package structure without a lead frame.

[0075] The embodiment of the present invention provides a method for preparing a semiconductor packaging structure without a lead frame, referring to Figure 2 As shown, the preparation method mainly comprises:

[0076] 201. Performing electroplating operation on the segmented area on the upper surface of the copper sheet substrate 800 to form a metal substrate 100 including a gold electroplating layer 101 and a copper electroplating layer 102, wherein the segmented area includes two external connection pin areas 100-1 and at least one chip bonding area 100-2;

[0077] 202. Arrange at least one chip on the upper surface of the chip bonding area 100-2 through the chip bonding material 200, the chip bonding area 100-2 at least covers the area corresponding to the chip, and interconnect the chip and the external connection pin area 100-1 through the bonding wire 300;

[0078] 203. Encapsulate the metal substrate 100, the chip and the bonding wire 300 with the encapsulation material 700, and expose the encapsulation material 700 to the outside of at least one side of the two external connection pin regions 100-1 facing outwards;

[0079] 204. Remove the copper substrate 800 by etching.

[0080] In this embodiment, the segmented areas on the upper surface of the copper substrate are set according to actual needs, that is, they are pre-set according to the number and size of chips included in the semiconductor packaging structure.

[0081] In this embodiment, the chip includes a control chip, a power MOSFET chip and a driver chip, so three chip bonding areas are correspondingly provided.

[0082] Furthermore, the segmentation region further includes at least one interconnection line region 100 - 3 , and the chip, the external connection pin region 100 - 1 and the interconnection line region 100 - 3 are interconnected through bonding wires 300 .

[0083] Specifically, the interconnection line area is used to replace a portion of bonding wires that have a large span or may cross wires, and it can also replace bonding wires to pass larger currents. Therefore, in general, if the interconnection relationship between each chip and the external connection pin area can be completed only by bonding wires and the overcurrent capacity can be achieved, there is no need to set up an interconnection line area separately.

[0084] In this embodiment, an interconnection line region is arranged between two chip bonding regions where the power MOSFET chip and the driver chip are arranged respectively.

[0085] Furthermore, the above step 201 can be specifically implemented as follows:

[0086] 2011. Coating photoresist on the upper surface of the copper substrate 800 to form a photoresist layer 900;

[0087] 2012. Removing the portion of the photoresist layer 900 located above the segmentation area through a development process to form at least one photoresist window area 901;

[0088] 2013. Performing gold electroplating and copper electroplating in the photoresist window area 901 in sequence to form a metal substrate 100 including a gold electroplating layer 101 and a copper electroplating layer 102;

[0089] 2014. Remove the remaining portion on the photoresist layer 900.

[0090] Reference Figure 3 to Figure 14 As shown, refer to Figure 3 to Figure 14 A specific implementation process of a method for preparing a semiconductor packaging structure without a lead frame is provided. Figure 3 to Figure 14 The entire preparation method can be further understood in detail.

[0091] like Figure 3 As shown, the figure shows the structure of the copper substrate without any treatment, and the copper substrate is a whole piece of thin copper plate.

[0092] like Figure 4 As shown, photoresist is evenly coated on the upper surface of the copper substrate to form a photoresist layer with uniform thickness.

[0093] like Figure 5 As shown, the portion of the photoresist layer located above the segmentation area is removed through a development process to form a plurality of mutually independent photoresist window areas.

[0094] like Figure 6 As shown, a gold electroplating operation is performed in each photoresist window area to form a gold electroplating layer in the photoresist window area, and the gold electroplating layer covers the upper surface of the copper substrate.

[0095] like Figure 7As shown, copper electroplating operation is performed again in each photoresist window area to form a copper electroplating layer in the photoresist window area. The copper electroplating layer covers the upper surface of the gold electroplating layer. These two electroplating layers form the metal substrate in the aforementioned leadless frame semiconductor packaging structure.

[0096] like Figure 8 As shown, after the two electroplating operations are completed, the remaining part of the photoresist layer is removed, so that the metal substrate formed above is divided into a number of independent divided areas, and the divided areas include two external connection pin areas, a number of chip bonding areas and a number of interconnection line areas.

[0097] like Fig. 9 As shown, the chip bonding material is printed sequentially on the upper surface of each chip bonding area.

[0098] like Fig.10 As shown, each chip is respectively arranged on the upper surface of the corresponding chip bonding area through the chip bonding material. The chip bonding area should at least cover the area corresponding to the chip. The arranged chips include a control chip, a power MOSFET chip and a driver chip.

[0099] like Fig.11 As shown, the control chip, the power MOSFET chip, the driver chip, the two external connection pin areas and the interconnection line area are interconnected by bonding wires.

[0100] like Fig.12 As shown, the metal substrate, chip and bonding wires are packaged by packaging materials.

[0101] It should be noted that in actual production, the copper sheet substrate will contain multiple products arranged in a matrix, and multiple products are processed together as a mold. Therefore, in the above packaging process, the packaging material is not exposed on the relatively outward side of the two external connection pin areas, and further dicing processing is required.

[0102] like Fig.13 As shown, the copper substrate under the packaging material is removed by etching.

[0103] like Fig.14 As shown, the semiconductor package structure completed by the above packaging is tested. After the test is completed, it is cut by dicing along the dotted lines shown in the figure, so that the packaging material is exposed on the opposite side of the two external connection pin areas to form an independent product. The final semiconductor package structure product is as shown in FIG. Figure 1 shown.

[0104] The lead frame-free semiconductor packaging structure and the preparation method thereof provided in the embodiments of the present invention improve the existing lead frame-based semiconductor packaging structure and the corresponding preparation method thereof. In the entire packaging process and the bill of materials, there is no lead frame required for traditional packaging. Instead, a chip bonding area, an interconnection line area, and an external connection pin area are grown on a thin copper sheet, thereby achieving a smaller volume and higher device density than a traditional lead frame-based semiconductor packaging structure, and the preparation process also has higher efficiency and lower cost.

[0105] At the same time, compared with the traditional semiconductor packaging structure in which each chip is separate and needs to be further integrated, it has the characteristics of high integration, easy use and high reliability.

[0106] It should be noted that, for the sake of simplicity, the embodiments of the above method are described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the present invention.

[0107] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0108] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "setting", "installation" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0109] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A lead frame-less semiconductor packaging structure, characterized in that: include: A metal substrate, which is divided into at least one divided area independent of each other, each of the divided areas includes two external connection pin areas and at least one chip bonding area; At least one chip, which is respectively arranged on the upper surface of the chip bonding area, the chip bonding area at least covers the area corresponding to the chip, and the chip and the external connection pin area are interconnected through bonding wires; A packaging material, which packages the metal substrate, the chip and the bonding wires, and exposes the packaging material to the outside of at least one side of the two external connection pin regions facing outwards; The segmentation area further includes at least one interconnection circuit area, and the chip, the external connection pin area and the interconnection circuit area are interconnected through the bonding wires; The metal substrate comprises a gold electroplating layer and a copper electroplating layer, wherein the copper electroplating layer is located above the gold electroplating layer; The thickness of the gold electroplating layer is 0.9-1.1 μm, and the thickness of the copper electroplating layer is 100-200 μm.

2. The packaging structure according to claim 1, characterized in that: A chip bonding material is also arranged between the upper surface of the chip bonding area and the chip.

3. The packaging structure according to claim 2, characterized in that: The chip bonding material is at least one of conductive glue, silver paste or solder paste.

4. The packaging structure according to claim 1, characterized in that: The chips include a control chip, a power MOSFET chip and a driver chip.

5. A method for preparing a lead frame-free semiconductor packaging structure, characterized in that: include: Performing electroplating operation on the segmented area on the upper surface of the copper sheet substrate to form a metal substrate including a gold electroplating layer and a copper electroplating layer, wherein the segmented area includes two external connection pin areas and at least one chip bonding area; Disposing at least one chip on the upper surface of the chip bonding area through a chip bonding material, the chip bonding area at least covers the area corresponding to the chip, and interconnecting the chip and the external connection pin area through bonding wires; Encapsulating the metal substrate, the chip and the bonding wires with an encapsulation material, and exposing the encapsulation material to at least one side of the two external connection pin regions facing outwards; Corrosion removes the copper substrate; The segmentation area further includes at least one interconnection line area, and the chip, the external connection pin area and the interconnection line area are interconnected through the bonding wires; The metal substrate comprises a gold electroplating layer and a copper electroplating layer, wherein the copper electroplating layer is located above the gold electroplating layer; The thickness of the gold electroplating layer is 0.9-1.1 μm, and the thickness of the copper electroplating layer is 100-200 μm.

6. The preparation method according to claim 5, characterized in that: The electroplating operation is performed on the segmented areas on the upper surface of the copper sheet substrate to form a metal substrate including a gold electroplating layer and a copper electroplating layer, comprising: Coating a photoresist on the upper surface of the copper substrate to form a photoresist layer; Removing the portion of the photoresist layer located above the segmentation area by a development process to form at least one photoresist window area; Performing gold electroplating and copper electroplating in sequence in the photoresist window area to form a metal substrate including a gold electroplating layer and a copper electroplating layer; The remaining portion on the photoresist layer is removed.

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