Silicon-based micromodule plastic packaging structure and preparation method thereof

Abstract

The present invention provides a silicon-based micromodule plastic packaging structure and a preparation method thereof, which can take into account both excellent electrical performance and strong mechanical performance, give full play to the advantages of high wiring density of TSV silicon transfer substrate, good thermal matching with semiconductor chips, high multi-chip integration density, high yield rate and good economy. It includes a TSV silicon transfer substrate, at least one chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate, passive components on the upper surface of the TSV silicon transfer substrate, and a plastic packaging body encapsulated on the other five surfaces except the lower surface of the TSV silicon transfer substrate; wherein the back of the chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate is exposed outside the plastic packaging body, the backs of multiple chips or composite chips and the backs of the chips or composite chips and the plastic packaging body surface on the upper surface of the TSV silicon transfer substrate are all in the same plane, and the surface of the passive components is lower than the back of the chip or composite chip on the upper surface of the TSV silicon transfer substrate.

Description

Technical Field

[0001] The present invention belongs to the technical field of advanced electronic packaging, and in particular relates to a silicon-based micromodule plastic packaging structure and a preparation method thereof. Background Art

[0002] Driven by the demand for consumer electronic products, such as smartphones and tablets, the packaging of electronic products is developing towards thinness, smallness and low cost. At present, the advanced packaging methods related to 2.5D and 3D have attracted the attention of the industry and have achieved certain development results. However, the advanced packaging design based on silicon vias faces many technical difficulties and the dilemma of high cost.

[0003] In the prior art, for advanced packaging structures, the domestic patent "A method for manufacturing a fan-out 2.5D / 3D packaging structure based on a carrier" (patent number 201510970167.5) discloses a method for plastic packaging of a flip-chip bare chip or a multi-layer chip assembly on a TSV adapter board. First, a TSV adapter board with multi-layer rewiring only on the front side is prepared, the back side of the TSV adapter board is thinned, copper plating is exposed, and singulation is performed. The front side of the TSV adapter board is covered with a carrier board facing up, and the chip is flipped onto each adapter board and then plastic-sealed. After plastic packaging, a passivation layer, a seed layer, a rewiring layer, and a UBM bottom metal layer are repeatedly made on the back side of the adapter board. The current technology has the following problems:

[0004] (1) After plastic encapsulation, the thermal expansion coefficient of the plastic powder is quite different from that of the TSV adapter board and the chip. Therefore, not only will the plastic encapsulation body (in sheet form) have a certain warping after returning to room temperature after the plastic encapsulation process is completed, but in the subsequent back passivation layer, seed layer, rewiring layer, and UBM bottom metal layer processes, the warping will be further aggravated as the process temperature changes. The warping will increase the difficulty of implementing the wafer process, such as exposure defocus and uniformity of PVD metal deposition, affecting the process quality and even causing the process to fail to be implemented normally. This method of replacing the silicon wafer preparation technology of the metal rewiring layer on the back of the TSV transfer substrate with the fan-out technology encapsulated by plastic powder has a certain loss in wiring accuracy and wiring density. Obviously, the line accuracy of the fan-out technology cannot be compared with that of the silicon wafer technology. In addition, it loses the possibility of using inorganic media such as silicon dioxide and silicon nitride on the back of the transfer substrate as the electrical insulating material between the metal layers and using the Damascus process to prepare the metal rewiring layer with ultra-fine line width (sub-micron and below), which cannot meet the demand for ultra-high density wiring of future products.

[0005] (2) The chip not only has to withstand the plastic encapsulation process, but also has to endure the risks and process yield loss brought by the rewiring process on the back of the adapter board, which will cause cost pressure for expensive chips.

[0006] (3) Before the chip is flipped, the TSV adapter board has only completed multi-layer rewiring on the front side and exposed copper on the back side of the TSV hole. It is a semi-finished product. It is impossible to test the electrical interconnection of the TSV adapter board before or after singulation. In other words, it is impossible to judge the quality of the corresponding TSV adapter board when the chip is flipped. It is a blind mounting method. There is a possibility that a good chip will be flipped onto a bad substrate, which will cause a certain amount of chip waste and cause cost pressure.

[0007] (4) Since the current plastic powder materials cannot withstand temperatures of 250°C or above for a long time, and the organic electrical insulating materials between metal layers generally need to be kept at a constant temperature of 250°C or above for 1 hour to fully cure, when the above patented method is used, the organic electrical insulating materials between the wiring layers on the back of the adapter board can only be cured at a lower temperature of no more than 250°C, which makes it difficult to fully cure, resulting in a loss of electrical and mechanical properties of the final organic electrical insulating layer, thereby affecting the performance of the entire packaging structure. Summary of the invention

[0008] In order to solve the problems existing in the prior art, the present invention provides a silicon-based micromodule plastic packaging structure and a preparation method thereof. The obtained TSV silicon-based micromodule can take into account both excellent electrical properties and strong mechanical properties, give full play to the advantages of high wiring density of TSV silicon transfer substrate, good thermal matching with semiconductor chips, and high multi-chip integration density, and has a high yield and good economy.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] A silicon-based micromodule plastic packaging structure, comprising

[0011] A TSV silicon transfer substrate, at least one chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate, passive components arranged on the upper surface of the TSV silicon transfer substrate, and a plastic package encapsulated on the other five surfaces except the lower surface of the TSV silicon transfer substrate;

[0012] The back of the chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate is exposed outside the plastic package, and the backs of the multiple chips or composite chips and the backs of the chips or composite chips and the plastic package surface on the upper surface of the TSV silicon transfer substrate are all in the same plane;

[0013] The passive components are surface mount passive components or chip passive components; the passive components are wrapped by a plastic package, and the surface of the passive components is lower than the back of the chip or composite chip on the upper surface of the TSV silicon transfer substrate.

[0014] Preferably, it also includes at least one chip or composite chip flipped on the lower surface of the TSV silicon transfer substrate.

[0015] Preferably, the TSV silicon transfer substrate includes a TSV through hole penetrating the silicon substrate, a multi-layer metal rewiring layer on the upper surface, a multi-layer metal rewiring layer on the lower surface, an upper surface under-bump metal pad layer and a lower surface under-bump metal pad layer, and the chip or composite chip is flip-bonded to the upper surface under-bump metal pad layer through the flip-chip bumps thereon.

[0016] Preferably, the pad diameter of the under bump metal pad layer on the lower surface of the TSV silicon transfer substrate is larger than the pad diameter of the under bump metal pad layer on the upper surface of the TSV silicon transfer substrate.

[0017] Preferably, the plastic sealing body adopts a plastic sealing material with a thermal expansion coefficient less than 10ppm / °C;

[0018] The plastic package wrapped around the side of the TSV silicon transfer substrate has a lateral thickness of less than 100 microns.

[0019] Preferably, the composite chip is a 3D chip formed by pre-TSV stacking and integration of multiple chips, or a 2.5D chip formed by pre-integration of multiple chips on another TSV silicon transfer substrate, or a 2D chip formed by pre-integration of multiple chips through Fan-out technology.

[0020] A method for preparing a silicon-based micromodule plastic packaging structure comprises the following steps:

[0021] Prepare TSV silicon transfer substrate, perform basic test on TSV silicon transfer substrate, if pass the test, proceed to the next step;

[0022] Surface assembly of passive components on TSV silicon interposer substrate;

[0023] Micro-assemble chips or composite chips on the TSV silicon transfer substrate to form a TSV silicon bare micro-module;

[0024] Conduct electrical interconnection characteristic test on TSV silicon bare micromodule, if it passes the test, proceed to the next step;

[0025] Plastic-sealing the remaining surfaces of the TSV bare silicon micromodule except the lower surface of the TSV silicon transfer substrate to form a TSV silicon-based micromodule plastic-sealed body;

[0026] Thinning the surface of the plastic package on the upper surface of the TSV silicon transfer substrate until at least the back side of the chip or composite chip is exposed;

[0027] Conduct electrical interconnection characteristic test on the thinned TSV silicon-based micromodule plastic package. If it passes the test, proceed to the next step;

[0028] The thinned TSV silicon-based micromodule plastic package body is ball-planted and sliced, and a silicon-based micromodule plastic package structure is prepared.

[0029] Preferably, during the plastic encapsulation, the bare micromodules that have passed the test are temporarily mounted on the sheet carrier in sequence to form a two-dimensional array of bare micromodules on the sheet carrier, and the side of the sheet carrier on which the bare micromodules are temporarily mounted is encapsulated with a plastic encapsulation material to form a TSV silicon-based micromodule plastic encapsulation body;

[0030] During ball planting, the ball planting operation is performed only on the under-bump metal pad on the lower surface of the TSV silicon transfer substrate of the TSV silicon-based micromodule plastic package that has passed the test.

[0031] Preferably, the basic test on the TSV silicon transfer substrate at least includes an appearance test and a double-sided electrical continuity test.

[0032] Preferably, before ball planting, the method further includes micro-assembling a chip or a composite chip on the lower surface of the TSV silicon transfer substrate.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention provides a silicon-based micromodule plastic sealing structure, which assembles chips on a prepared TSV silicon transfer substrate and performs plastic sealing, which can fully give play to the advantages of the TSV silicon transfer substrate with high wiring density, good thermal matching with semiconductor chips, and high multi-chip integration density, and solves the shortcomings of the TSV silicon transfer substrate integrated microcomponents being brittle and fragile. At the same time, passive components are provided, and the surface mounting integration of the passive components on the upper surface of the TSV silicon transfer substrate is more conducive to improving the electrical performance of the micromodule. Therefore, the structure of the present invention enables the TSV silicon-based micromodule finally obtained to have both excellent electrical performance and strong mechanical performance as a whole. At the same time, the mounting method and heat dissipation method in subsequent applications are compatible with traditional BGA devices, which is more conducive to being accepted by users. In addition, the structure of the present invention enhances the mechanical strength of the TSV silicon-based micromodule, so that the conventional test aging method using a pin array fixture can be realized, which can effectively solve the testing, aging and screening problems of the TSV silicon-based micromodule. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the cross-sectional structure of the TSV silicon transfer substrate of the present invention;

[0036] Figure 2 It is a schematic diagram of the cross-sectional structure of a bare micromodule after chips and passive components are assembled on the surface of the TSV silicon transfer substrate of the present invention;

[0037] Figure 3 It is a schematic diagram of the cross-sectional structure of the plastic-sealed body of the TSV silicon-based bare micromodule of the present invention after the plastic-sealing process is completed;

[0038] Figure 4 It is a schematic diagram of the cross-sectional structure of the TSV silicon-based micromodule plastic package after thinning of the present invention;

[0039] Figure 5 It is a schematic diagram of the cross-sectional structure of the TSV silicon-based micromodule plastic package after ball implantation of the present invention;

[0040] Figure 6 It is a schematic diagram of the cross-sectional structure of the TSV silicon-based micromodule plastic package body after dicing and cutting of the present invention;

[0041] Figure 7 is a schematic cross-sectional structure diagram of a TSV silicon-based micromodule in Example 2 of the present invention;

[0042] Figure 8 1 is a schematic cross-sectional structure diagram of a third embodiment of a TSV silicon-based micromodule in Embodiment 3 of the present invention;

[0043] Fig. 9 is a process flow chart of TSV silicon-based micromodules of embodiments 1 and 2 of the present invention;

[0044] Fig.10 It is a process flow chart of TSV silicon-based micromodule according to embodiment 3 of the present invention.

[0045] In the figure, silicon substrate 1, TSV through hole 2, upper surface multi-layer metal rewiring layer 3, upper surface metal interlayer dielectric layer 4, lower surface multi-layer metal rewiring layer 5, lower surface metal interlayer dielectric layer 6, upper surface under-bump metal pads 7, 8, upper surface surface mount pads 9, lower surface under-bump metal pads 10, flip chips 11, 12, 22, 23, passive components 13, flip-chip bumps 14, 15, solder joints 16, bottom filling material 17, plastic encapsulation material 18, solder balls 19, TSV interconnect 20, composite chip 21, TSV silicon transfer substrate 100, bare micromodule 200. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention; the following embodiments are only embodiments of a part of the present invention, rather than all embodiments, and are not intended to limit the scope of the present invention.

[0047] The present invention provides a silicon-based micromodule plastic packaging structure, comprising:

[0048] TSV silicon transfer substrate 100, at least one chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate, passive components 13 arranged on the upper surface of the TSV silicon transfer substrate, and a plastic package encapsulated on the other five surfaces except the lower surface of the TSV silicon transfer substrate;

[0049] The back of the chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate is exposed outside the plastic package, and the backs of the multiple chips or composite chips and the backs of the chips or composite chips and the plastic package surface on the upper surface of the TSV silicon transfer substrate are all in the same plane;

[0050] The passive component 13 is a patch passive component or a chip passive component, but not limited thereto; the passive component 13 includes a capacitor, a resistor, an inductor, etc., but not limited thereto; the passive component 13 is wrapped by a plastic package, that is, the upper surface of the passive component 13 is lower than the surface of the plastic package, and the surface of the passive component 13 is lower than the back of the chip or composite chip on the upper surface of the TSV silicon transfer substrate;

[0051] The present invention provides a silicon-based micromodule plastic sealing structure, which assembles chips on a prepared TSV silicon transfer substrate 100 and performs plastic sealing, which can fully give play to the advantages of high wiring density, good thermal matching with semiconductor chips, and high multi-chip integration density of the TSV silicon transfer substrate, and solve the shortcomings of brittle and fragile integrated microcomponents of the TSV silicon transfer substrate. At the same time, a passive component 13 is provided, and the surface mounting integration of the passive component 13 on the upper surface of the TSV silicon transfer substrate is more conducive to improving the electrical performance of the micromodule. Therefore, the structure of the present invention enables the TSV silicon-based micromodule finally obtained to have both excellent electrical performance and strong mechanical performance as a whole. At the same time, the mounting method and heat dissipation method in subsequent applications are compatible with traditional BGA devices, which is more conducive to being accepted by users. In addition, the structure of the present invention enhances the mechanical strength of the TSV silicon-based micromodule, so that the conventional test aging method using a pin array fixture can be realized, which can effectively solve the testing, aging and screening problems of the TSV silicon-based micromodule.

[0052] In this embodiment 3, at least one chip or composite chip is flipped on the lower surface of the TSV silicon transfer substrate.

[0053] Among them, the TSV silicon transfer substrate 100 includes a TSV through hole 2 penetrating the silicon substrate, a multi-layer metal rewiring layer 3 on the upper surface, a multi-layer metal rewiring layer 5 on the lower surface, an upper surface under-bump metal pad layer and a lower surface under-bump metal pad layer, and the chip or composite chip is flip-bonded to the under-bump metal pad layer on the upper surface through the flip-chip bumps thereon.

[0054] Further, a pad diameter of an under bump metal (UBM) pad layer on the lower surface of the TSV silicon transfer substrate is greater than a pad diameter of an under bump metal (UBM) pad layer on the upper surface of the TSV silicon transfer substrate.

[0055] The surface of the passive element 13 is lower than the back side of the chip or composite chip on the upper surface of the TSV silicon transfer substrate.

[0056] Preferably, the plastic packaging body adopts a plastic packaging material with a thermal expansion coefficient less than 10 ppm / °C.

[0057] Preferably, the lateral thickness of the plastic package wrapped around the side of the TSV silicon transfer substrate 100 is preferably less than 100 microns.

[0058] Preferably, the composite chip is a 3D chip formed by pre-TSV stacking and integration of multiple chips, or a 2.5D chip formed by pre-integration of multiple chips on another TSV silicon transfer substrate, or a 2D chip formed by pre-integration of multiple chips through Fan-out technology.

[0059] The present invention solves the surface flattening problem when multiple chips are flip-chip integrated on a TSV silicon transfer substrate. When multiple chips are flip-chip integrated on a TSV silicon transfer substrate, due to inconsistent thickness between chips, or inconsistent solder ball heights of chips, or due to process errors when flipping chips, the backs of chips are not on the same plane, which will cause a series of problems. For example, the current flip-chip and mounting equipment all use vacuum suction heads to pick up the operation objects. The backs of chips are uneven, and may not be picked up by the vacuum suction heads because they cannot provide a flat suction surface for the vacuum suction heads; and usually a heat sink needs to be attached to the back of the chip. When multiple chips are flip-chip integrated on a TSV silicon transfer substrate, because the gap between chips is small, a separate heat sink cannot be used. Usually, an integral heat sink needs to be used to fit the back of each chip at the same time. The uneven backs of each chip increase the design and processing of the heat sink, as well as the difficulty of mounting the heat sink.

[0060] The structure provided by the present invention can solve the problems of testing, aging and screening of TSV silicon-based micromodules. The current conventional KGD fixture can be used for testing, aging and screening. On the one hand, the present invention makes the backs of multiple chips flipped on the TSV silicon transfer substrate on the same plane, avoiding the uneven distribution of the pressure applied by the cover plate of the KGD fixture on the backs of each chip, resulting in excessive pressure on one or some chips, or excessive pressure at certain local positions of the chip, causing the chip to be cracked; on the other hand, the TSV silicon transfer substrate itself is thin and brittle. If the cover plate of the KGD fixture only applies downward pressure on the back of one or more chips flip-chip integrated on the TSV silicon transfer substrate, the pin array of the KGD fixture applies upward pressure on the surface of the TSV silicon transfer substrate away from the chip, which is easy to break the TSV silicon transfer substrate.

[0061] The structure provided by the present invention has lower chip heat dissipation thermal resistance, and at the same time makes it easier to apply a heat sink or a heat dissipation cold plate when the micromodule is used, and the heat dissipation effect of the micromodule is better. On the one hand, the substrate material on the back of the chip is exposed by thinning the back after plastic packaging, so that it can directly contact with the heat sink, reducing the thermal resistance between the back of the chip and the heat sink, and at the same time, the chip becomes thinner, further reducing the thermal resistance from the chip active area to the back of the chip; on the other hand, in the present invention, the back of the chip is flush with the surface of the plastic packaging material, and the most conventional sheet heat sink can be used, or it can be directly in contact with the heat dissipation cold plate at the system level; secondly, the chip is filled with plastic packaging material, and the thermal conductivity of the plastic packaging material is better than that of air. The plastic packaging material around the chip provides an additional heat dissipation channel for the chip.

[0062] like Fig. 9 As shown, a method for preparing a silicon-based micromodule plastic packaging structure includes the following steps:

[0063] Prepare a TSV silicon transfer substrate 100, perform a basic test on the TSV silicon transfer substrate 100, and proceed to the next step if the test is passed;

[0064] Surface assembling passive components 13 on the TSV silicon transfer substrate;

[0065] The TSV silicon bare micromodule 200 is assembled by flipping the chip or composite chip on the upper surface of the TSV silicon transfer substrate;

[0066] Conducting an electrical interconnection characteristic test on the TSV silicon bare micromodule 200, and if the test is passed, proceeding to the next step;

[0067] Plastic-sealing the remaining surfaces of the TSV bare silicon micromodule 200 except the lower surface of the TSV silicon transfer substrate to form a TSV silicon-based micromodule plastic-sealed body;

[0068] Thinning the surface of the plastic package on the upper surface of the TSV silicon transfer substrate until at least the back side of the chip or composite chip is exposed;

[0069] Conduct electrical interconnection characteristic test on the thinned TSV silicon-based micromodule plastic package. If it passes the test, proceed to the next step;

[0070] The thinned TSV silicon-based micromodule plastic package is ball-planted and sliced ​​to complete the preparation.

[0071] Preferably, during the plastic encapsulation, the bare micromodules 200 that have passed the test are temporarily mounted on the sheet carrier in sequence to form a two-dimensional array of bare micromodules 200 on the sheet carrier, and then the side of the sheet carrier on which the bare micromodules 200 are temporarily mounted is encapsulated with a plastic encapsulation material to form a TSV silicon-based micromodule plastic encapsulation body.

[0072] Preferably, during ball planting, the ball planting operation is performed only on the under bump metal (UBM) pads on the lower surface of the TSV silicon transfer substrate of the TSV silicon-based micromodule plastic package that has passed the test.

[0073] The basic test on the TSV silicon transfer substrate 100 at least includes an appearance test and a double-sided electrical continuity test.

[0074] In the present embodiment 3, before ball planting, it also includes micro-assembling chips or composite chips on the lower surface of the TSV silicon transfer substrate.

[0075] Embodiment 1, attached Figure 1-6 A schematic diagram of the cross-sectional structure of each stage in the preparation process of Example 1 is given.

[0076] Step 1, such as Figure 1 As shown, a TSV silicon transfer substrate 100 is prepared, and a TSV through hole 2 penetrates the silicon substrate 1 to achieve electrical interconnection between the multi-layer metal rewiring layer 3 on the upper surface of the TSV silicon transfer substrate and the multi-layer metal rewiring layer 5 on the lower surface of the TSV silicon transfer substrate.

[0077] Among them, the aperture of the TSV through hole 2 is 5 microns-50 microns, and the thickness of the silicon substrate 1 is 70 microns-300 microns; the multi-layer metal rewiring layer 3 on the upper surface of the TSV silicon transfer substrate and the multi-layer metal rewiring layer 5 on the lower surface of the TSV silicon transfer substrate include at least one metal rewiring layer.

[0078] The under bump metal (UBM) pads 7 and 8 on the upper surface of the TSV silicon transfer substrate are circular pads, and the pad diameter, number and arrangement thereof depend on the size of the bumps of the chips 11 and 12 to be flipped.

[0079] The pad diameters of the under bump metal (UBM) pads 7 and 8 on the upper surface of the TSV silicon transfer substrate may be equal or different.

[0080] The pad size and arrangement of the surface mount pads 9 on the upper surface of the TSV silicon transfer substrate depend on the specification size of the passive components 13 to be surface mounted.

[0081] Preferably, the surface mount pad 9 is in the shape of a rectangle with the top corners cut off.

[0082] The under-bump metal pads 7 and 8 on the upper surface of the TSV silicon transfer substrate and the surface mount pad 9 are located in the same layer and adopt the same metal material structure to facilitate process preparation.

[0083] Preferably, the metal material structure of the under bump metal pad is a combination of copper, nickel and gold.

[0084] The under-bump metal pad 10 on the lower surface of the TSV silicon transfer substrate is a circular pad used for external solder ball pins of the micromodule.

[0085] After the TSV silicon transfer substrate 100 is prepared, at least an appearance test and a double-sided electrical continuity test need to be performed on the TSV silicon transfer substrate 100 to determine whether the TSV silicon transfer substrate 100 can be used in subsequent micro-assembly processes.

[0086] Step 2, such as Figure 2 As shown, the passive component 13 is micro-assembled on the upper surface of the TSV silicon transfer substrate by surface mounting, solder paste is applied in advance on the metal pad 9 under the bump on the upper surface of the TSV silicon transfer substrate, the passive component 13 is mounted, and after thermal reflow, a solder joint 16 is formed between the electrode of the passive component 13 and the pad 9;

[0087] The flip chip 11 is flip-bonded to the under-bump metal pad 7 on the upper surface of the TSV silicon transfer substrate through the flip bump 14 thereon, so as to complete the micro-assembly of the flip chip 11 to the upper surface of the TSV silicon transfer substrate;

[0088] The flip chip 12 is flip-bonded to the under-bump metal pad 8 on the upper surface of the TSV silicon transfer substrate through the flip bump 15 thereon, thereby completing the micro-assembly of the flip chip 12 to the upper surface of the TSV silicon transfer substrate;

[0089] Furthermore, the chip micro-assembly method is flip-chip bonding, and at least one chip is flip-chip bonded, and the chip flip-chip bonding includes bump bonding, application of bottom filling material 17, and the like.

[0090] The TSV silicon transfer substrates entering the micro-assembly process are all TSV silicon transfer substrates that have passed the test, and the test content at least includes a double-sided electrical continuity test.

[0091] The highest point of the passive component 13 after surface mounting is lower than the backside of the chips 11 and 12 after flip-chip bonding.

[0092] Furthermore, after completing the micro-assembly of the flip chips 11 and 12, and the passive component 13 on the upper surface of the TSV silicon transfer substrate, it is necessary to test the electrical interconnection characteristics of the assembled bare micromodule 200 to determine the quality of the above-mentioned microassembly and whether the bare micromodule 200 can be used for the subsequent plastic packaging process.

[0093] Step three, temporarily mount the qualified bare micromodules 200 on the sheet carrier in sequence to form a two-dimensional array of bare micromodules 200 on the sheet carrier, and then use a plastic packaging material to encapsulate the side of the sheet carrier where the bare micromodules 200 are temporarily mounted.

[0094] The thickness of the formed plastic encapsulation body is greater than the maximum thickness of the bare micromodule 200, and the upper surface of the plastic encapsulation layer formed by the plastic encapsulation is flat.

[0095] All exposed surfaces of the bare micromodule 200 after temporary mounting are immersed in the plastic packaging material, and finally the sheet carrier is removed to expose the lower surface of the TSV silicon transfer substrate in the bare micromodule 200, forming a Figure 3 The structure shown.

[0096] Preferably, a plastic encapsulation material with a thermal expansion coefficient of less than 10 ppm / °C is used to reduce the risks of warping, delamination, etc. caused by thermal mismatch during the process.

[0097] In the above-mentioned plastic encapsulation process, the lower surface of the TSV silicon transfer substrate in the bare micromodule 200 faces the sheet carrier, and the temporary mounting accuracy of the bare micromodule 200 is preferably controlled within ±20 microns.

[0098] Preferably, according to different plastic packaging equipment used, the sheet carrier may be circular similar to the shape of a silicon wafer, or rectangular similar to the shape of a plastic packaging organic carrier, but is not limited thereto.

[0099] Preferably, the sheet carrier may be made of silicon, glass, organic material, metal, etc., but is not limited thereto.

[0100] Among them, since the thickness of the above-mentioned plastic packaging body is much smaller than its transverse dimension, the above-mentioned plastic packaging body is still in sheet shape.

[0101] Step 4: Figure 3 The plastic package shown is thinned from the surface near the back of the flip chip, as shown in Figure 4 As shown, until at least the back side of the flip chip is exposed.

[0102] The heat dissipation channel of the flip chip is mainly through the back of the chip, and after the plastic encapsulation process, the back of the flip chip is still some distance away from the top of the plastic encapsulation body. The back of the flip chip cannot directly contact the heat sink, and the thermal conductivity of the plastic encapsulation material itself is poor, which leads to an increase in the thermal resistance between the flip chip and the external heat sink, and cannot meet the heat dissipation requirements of the flip chip with large power consumption. The functional layer of the flip chip is close to the surface where the chip flip bump is located. The heat generated by the functional layer needs to flow through the entire chip thickness to the back of the chip. The thermal resistance of the heat conduction process increases with the increase of chip thickness, so thinning the thickness of the flip chip can further reduce the thermal resistance and enhance the heat dissipation effect. In addition, thinning the back of the TSV silicon-based micromodule plastic encapsulation body is also conducive to reducing the thickness of the TSV silicon-based micromodule, meeting the demand for thinness of the TSV silicon-based micromodule.

[0103] Furthermore, the lower surface under-bump metal pad 10 of the TSV silicon transfer substrate is used as the signal feed-in and feed-out point. Figure 4 The TSV silicon-based micromodule plastic package with backside thinning shown is subjected to electrical interconnection testing to identify the quality of the TSV silicon-based micromodule and further determine whether subsequent ball planting is required on the TSV silicon-based micromodule.

[0104] Step 5: Figure 5 As shown, the TSV silicon-based micromodule is ball-planted, and the solder ball array composed of solder balls 19 serves as the external IO pins of the entire TSV silicon-based micromodule.

[0105] The ball diameter and ball spacing of the solder balls 19 are usually larger than the diameter and spacing of the flip-chip bumps, so as to reduce the difficulty of the mounting process in subsequent applications.

[0106] The melting point of the solder ball 19 is usually lower than that of the flip chip bumps, so as to avoid remelting of the chip bumps during subsequent application and mounting, which may bring reliability risks.

[0107] Furthermore, based on the test results of electrical interconnection of the TSV silicon-based micromodule plastic package after back-side thinning, balls can be planted only on the under bump metal (UBM) pads on the lower surface of the TSV silicon transfer substrate of the TSV silicon-based micromodule that has passed the test, thereby avoiding the waste of ball planting materials and ball planting process time caused by ball planting on bad micromodules.

[0108] Step 6: Figure 6 As shown, the TSV silicon-based micromodule is sliced.

[0109] The cut plastic package of the present invention retains a certain thickness of plastic package material on the side of the TSV silicon transfer substrate, so that the TSV silicon-based micromodule plastic package is covered and protected on five sides except the lower surface of the TSV silicon transfer substrate, thereby making up for the brittle and fragile defect of the TSV silicon transfer substrate.

[0110] Among them, the lateral thickness of the plastic encapsulation material on the side of the TSV silicon transfer substrate is preferably less than 100 microns. On the one hand, while providing sufficient protection for the silicon material on the side of the TSV silicon transfer substrate, the thermal stress caused by thermal mismatch between the silicon material and the plastic encapsulation material is further reduced. On the other hand, the increase in the lateral XY size of the TSV silicon-based micromodule caused by plastic encapsulation is reduced, thereby meeting the miniaturization requirements of the TSV silicon-based micromodule.

[0111] Example 2

[0112] The preparation process of this embodiment 2 is the same as that of embodiment 1. Figure 7 As shown, the flip chip bonded on the upper surface of the TSV silicon transfer substrate is a composite chip in which multiple chips are pre-integrated together. The composite chip 21 is formed by stacking multiple chip TSVs, and the multiple chips are electrically connected in the vertical direction through TSV interconnections 20 that pass through the chips.

[0113] Among them, the composite chip can be a 3D chip formed by pre-TSV stacking and integration of multiple chips, or a 2.5D chip formed by pre-integration of multiple chips on another TSV silicon transfer substrate, or a 2D chip formed by pre-integration of multiple chips through Fan-out technology, but is not limited to this.

[0114] Example 3

[0115] The preparation method of this embodiment 3 is as follows Fig.10 As shown, after the TSV silicon-based micromodule plastic package is formed, a flip chip 23 can be further flip-bonded on the lower surface of the TSV silicon transfer substrate of the TSV silicon-based micromodule, and the external solder balls 19 of the TSV silicon-based micromodule are distributed around the flip chip 23, and the thickness of the flip chip 23 and the size of the solder balls 19 are controlled, so that the height of the solder balls 19 is still higher than the back of the flip chip 23 after the subsequent application of the TSV silicon-based micromodule. The flip chip 23 is bonded to the under-bump metal pad on the lower surface of the TSV silicon transfer substrate through a bump array. Since the size of the solder ball 19 is larger than the bump size of the flip chip 23, the diameter of the under-bump metal (UBM) pad on the lower surface of the TSV silicon transfer substrate corresponding to the solder ball 19 is also correspondingly larger than the diameter of the under-bump metal pad on the lower surface of the TSV silicon transfer substrate corresponding to the flip chip 23.

[0116] The under bump metal (UBM) pads on the lower surface of the TSV silicon transfer substrates of the two diameters are preferably on the same metal layer, preferably have the same material structure, and are preferably prepared simultaneously.

[0117] The process method and steps for forming the five-sided encapsulated TSV silicon-based micromodule plastic package in this embodiment 3 are the same as the process method and steps disclosed in embodiments 1 and 2, except that for the TSV silicon-based micromodule plastic package that has passed the test, a chip must first be micro-assembled on the exposed lower surface of the TSV silicon transfer substrate, and the micro-assembly method is preferably flip-chip bonding. After completing the micro-assembly processes such as bump bonding and bottom filling of the flip chip, balls are planted on the TSV silicon-based micromodule plastic package, and the planted solder balls are distributed around the flip chip on the lower surface of the TSV silicon transfer substrate; finally, the TSV silicon-based micromodule plastic package is diced and cut to complete the preparation of the TSV silicon-based micromodule, and its structure is as shown in FIG. Figure 8 shown.

Claims

1. A method for preparing a silicon-based micromodule plastic packaging structure, characterized in that: The following steps are included: preparing a TSV silicon transfer substrate (100), performing a basic test on the TSV silicon transfer substrate (100), and if the test is passed, proceeding to the next step; Surface assembling passive components on the TSV silicon interposer substrate (13); Micro-assembling chips or composite chips on the upper surface of the TSV silicon transfer substrate to form a TSV silicon bare micro-module (200); Conducting an electrical interconnection characteristic test on the TSV silicon bare micromodule (200), and if the test passes, proceeding to the next step; Plastic-sealing the remaining surfaces of the TSV silicon bare micromodule (200) except the lower surface of the TSV silicon transfer substrate to form a TSV silicon-based micromodule plastic-sealed body; Thinning the surface of the plastic package on the upper surface of the TSV silicon transfer substrate until at least the back side of the chip or composite chip is exposed; Conduct electrical interconnection characteristic test on the thinned TSV silicon-based micromodule plastic package. If it passes the test, proceed to the next step; The thinned TSV silicon-based micromodule plastic package body is balled and sliced, and a silicon-based micromodule plastic package structure is prepared; The basic test on the TSV silicon transfer substrate (100) at least includes an appearance test and a double-sided electrical continuity test; The silicon-based micromodule plastic packaging structure comprises A TSV silicon transfer substrate (100), at least one chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate, a passive component (13) arranged on the upper surface of the TSV silicon transfer substrate, and a plastic package encapsulated on the other five surfaces except the lower surface of the TSV silicon transfer substrate; The back of the chip or composite chip flipped on the upper surface of the TSV silicon transfer substrate is exposed outside the plastic package, and the backs of the multiple chips or composite chips and the backs of the chips or composite chips and the plastic package surface on the upper surface of the TSV silicon transfer substrate are all in the same plane; The passive component (13) is a surface-mount passive component or a chip passive component; the passive component (13) is wrapped by a plastic package, and the surface of the passive component (13) is lower than the back side of the chip or composite chip on the upper surface of the TSV silicon transfer substrate; The plastic sealing body adopts a plastic sealing material with a thermal expansion coefficient less than 10ppm / ℃; The plastic package wrapped around the side of the TSV silicon transfer substrate has a lateral thickness of less than 100 microns.

2. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 1, characterized in that: It also includes at least one chip or composite chip flipped on the lower surface of the TSV silicon transfer substrate.

3. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 1, characterized in that: The TSV silicon transfer substrate (100) comprises a TSV through hole (2) penetrating a silicon substrate, an upper surface multi-layer metal rewiring layer (3), a lower surface multi-layer metal rewiring layer (5), an upper surface under-bump metal pad layer and a lower surface under-bump metal pad layer, wherein the chip or composite chip is flip-bonded to the upper surface under-bump metal pad layer via flip-chip bumps thereon.

4. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 3, characterized in that: The pad diameter of the under-bump metal pad layer on the lower surface of the TSV silicon transfer substrate is greater than the pad diameter of the under-bump metal pad layer on the upper surface of the TSV silicon transfer substrate.

5. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 1, characterized in that: The composite chip is a 3D chip formed by pre-TSV stacking and integration of multiple chips, or a 2.5D chip formed by pre-integration of multiple chips on another TSV silicon transfer substrate, or a 2D chip formed by pre-integration of multiple chips through Fan-out technology.

6. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 1, characterized in that: During the plastic encapsulation, the bare micromodules (200) that have passed the test are temporarily mounted on the sheet carrier in sequence to form a two-dimensional array of bare micromodules (200) on the sheet carrier, and the side of the sheet carrier on which the bare micromodules (200) are temporarily mounted is encapsulated with a plastic encapsulation material to form a TSV silicon-based micromodule plastic encapsulation body; When implanting the ball, the implanting operation is performed only on the metal pad under the bump on the lower surface of the TSV silicon transfer substrate (100) of the TSV silicon-based micromodule plastic package that has passed the test.

7. The method for preparing a silicon-based micromodule plastic packaging structure according to claim 1, characterized in that: Before ball planting, it also includes micro-assembling chips or composite chips on the lower surface of the TSV silicon transfer substrate.

Images