Semiconductor structure and method for forming the same
By forming a second trench larger than the first trench width in the semiconductor integrated circuit, the short circuit problem caused by the increase in the density of the conductive interconnect line is solved, and the electrical performance and structural reliability are improved.
Patent Information
- Application Number
- CN202010829677.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-08-18
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2040-08-18
AI Technical Summary
The increase in the density of conductive interconnects in semiconductor integrated circuits leads to short circuits, affecting device performance.
By forming a first trench on the substrate and partially filling the first fill layer, then etching the second trench on the dielectric layer, the first fill layer is removed, and finally depositing conductive material in the first trench and the second trench , a second trench larger than the first trench width is formed to match the height of the fill layer, avoiding excessive lateral etching of the dielectric layer by the etching process and preventing short circuits.
It effectively avoids the short circuit of conductive materials, improves the electrical performance of semiconductor structures, and improves contact performance and structural reliability.
Smart Images
Figure CN114078749B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] With the continuous development of semiconductor integrated circuit technology, the size of conductive interconnects in integrated circuits and the distance between conductive interconnects are constantly shrinking, resulting in a corresponding increase in the arrangement density of conductive interconnects. As the arrangement density of conductive interconnects increases, short circuits between conductive interconnects are likely to occur, resulting in reduced performance or even failure of semiconductor devices. Summary of the invention
[0003] Based on this, it is necessary to provide a semiconductor structure and a method for forming the same in order to address the problem that the semiconductor structure is prone to short circuits.
[0004] A method for forming a semiconductor structure, comprising:
[0005] providing a substrate;
[0006] forming a dielectric layer having a first trench on the substrate;
[0007] forming a first filling layer partially filling the first trench;
[0008] forming a first mask layer having a first opening on the dielectric layer, wherein the first opening exposes the first filling layer and a portion of the dielectric layer;
[0009] Using the first mask layer as a mask, etching the dielectric layer to form a second trench;
[0010] removing the first filling layer;
[0011] A conductive material is formed in the first trench and the second trench.
[0012] In one embodiment, forming a first filling layer in the first trench includes:
[0013] forming an initial first filling layer in the first trench and on the dielectric layer;
[0014] All of the initial first filling layer on the dielectric layer and part of the initial first filling layer in the first groove are etched back, and the remaining initial first filling layer serves as the first filling layer.
[0015] In one embodiment, the step of etching back all of the initial first filling layer on the dielectric layer and a portion of the initial first filling layer in the first trench, with the remaining initial first filling layer serving as the first filling layer, comprises:
[0016] Back-etching all of the initial first filling layer on the dielectric layer and part of the initial first filling layer in the first groove so that the height ratio of the first filling layer meets a preset range, and the remaining initial first filling layer serves as the first filling layer;
[0017] The height ratio is the ratio of the height of the first filling layer along a direction perpendicular to the substrate to the depth of the first groove.
[0018] In one embodiment, the substrate includes a first region and a second region, the first trench and the second trench are both located in the first region and the second region, and a density of the first trench in the first region is greater than a density of the first trench in the second region.
[0019] In one embodiment, the height ratio of the first filling layer is between 0.7 and 0.9.
[0020] In one embodiment, a ratio of the depth of the second groove to the depth of the first groove is between 0.5 and 0.8.
[0021] In one embodiment, a depth of the second trench in the second region is greater than a depth of the second trench in the first region.
[0022] In one embodiment, an etching selectivity ratio between the dielectric layer and the first filling layer is greater than 7.
[0023] In one embodiment, forming a first mask layer having a first opening on the dielectric layer, wherein the first opening exposes the first filling layer and a portion of the dielectric layer, comprises:
[0024] forming the first mask layer in the first trench and on the dielectric layer;
[0025] All of the first mask layer in the first trench and a portion of the first mask layer on the dielectric layer are removed.
[0026] In one embodiment, the first mask layer is a photoresist layer.
[0027] In one embodiment, etching the dielectric layer using the first mask layer as a mask to form a second trench includes:
[0028] The dielectric layer is etched using the first mask layer as a mask to form the second trench, wherein the depth of the second trench is less than the depth of the first trench, and the bottom of the second trench is lower than the top of the first filling layer.
[0029] In one of the embodiments, a height ratio of the first filling layer in the first region is greater than a height ratio of the first filling layer in the second region.
[0030] In one embodiment, a depth of the second trench in the second region is equal to a depth of the second trench in the first region.
[0031] A semiconductor structure is formed by using the semiconductor structure forming method as described above.
[0032] The semiconductor structure and its forming method, the semiconductor structure forming method comprises: providing a substrate; forming a dielectric layer having a first groove on the substrate; forming a first filling layer partially filling the first groove; forming a first mask layer having a first opening on the dielectric layer, the first opening exposing the first filling layer and part of the dielectric layer; etching the dielectric layer with the first mask layer as a mask to form a second groove; removing the first filling layer; forming a conductive material in the first groove and the second groove. The present invention forms the first groove first, partially fills the first filling layer in the first groove and removes it after forming the second groove, so that the height of the first filling layer can be matched with the arrangement density of the semiconductor structure, thereby avoiding excessive lateral etching of the dielectric layer by the etching process, thereby avoiding the short circuit phenomenon of the conductive material, and improving the electrical performance of the semiconductor structure. Moreover, the present invention forms a second groove with a larger width than the first groove by the etching process, so that the first groove and the second groove can be used together to deposit conductive materials to form a semiconductor structure with better contact performance and structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment;
[0034] Figure 2 A schematic cross-sectional view of a substrate 100 provided in one embodiment;
[0035] Figure 3 is a schematic cross-sectional view of the semiconductor structure after step S200;
[0036] Figure 4 is a schematic cross-sectional view of a semiconductor structure after step S300 of an embodiment;
[0037] Figure 5 is a schematic cross-sectional view of a semiconductor structure after step S400 of an embodiment;
[0038] Figure 6 is a schematic cross-sectional view of a semiconductor structure after step S500 of an embodiment;
[0039] Figure 7 for Figure 6A schematic top view of a semiconductor structure of an embodiment;
[0040] Figure 8 is a schematic cross-sectional view of a semiconductor structure after step S700 of an embodiment;
[0041] Fig. 9 is a schematic cross-sectional view of a semiconductor structure after step S800 of an embodiment;
[0042] Fig.10 A flowchart of a method for forming a semiconductor structure according to another embodiment;
[0043] Fig.11 is a schematic cross-sectional view of a semiconductor structure after step S310 of another embodiment;
[0044] Fig.12 is a schematic cross-sectional view of a semiconductor structure after step S410 of another embodiment;
[0045] Fig.13 is a schematic cross-sectional view of a semiconductor structure including a first region and a second region according to another embodiment;
[0046] Fig.14 It is a cross-sectional schematic diagram of a semiconductor structure in the prior art.
[0047] Component number description:
[0048] Substrate: 100; first conductive layer: 110; first dielectric layer: 120; first region: 130; second region: 140; dielectric layer: 200; first trench: 210; first filling layer: 211; initial first filling layer: 212; second trench: 220; first mask layer: 300; first opening: 310; first barrier layer: 400; second barrier layer: 500; second conductive layer: 600 DETAILED DESCRIPTION
[0049] In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. It should be noted that the present invention can be implemented in many different forms and is not limited to the embodiments described herein. The purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0051] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0052] Figure 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 1 In this embodiment, the method for forming a semiconductor structure includes steps S100 to S700.
[0053] S100: providing a substrate 100.
[0054] Figure 2 A cross-sectional schematic diagram of a substrate 100 provided in an embodiment, referring to Figure 2 In this embodiment, a first conductive layer 110 and a first dielectric layer 120 have been formed in the substrate 100. Exemplarily, the first conductive layer 110 may be, but is not limited to, a structure such as a conductive interconnection line. Exemplarily, when the first conductive layer 110 is a conductive interconnection line, the first conductive layer 110 may transmit an electrical signal to a semiconductor device in the substrate 100, such as a transistor. The first dielectric layer 120 is used to isolate adjacent first conductive layers 110, thereby avoiding short circuits or leakage currents between the first conductive layers 110, thereby improving the electrical reliability of the device. The first conductive layer 110 and the first dielectric layer 120 may be obtained by forming a groove in the substrate 100 and filling it, or may be obtained by directly depositing it on the surface of the substrate 100. The present embodiment does not specifically limit the method for forming the first conductive layer 110 and the first dielectric layer 120.
[0055] S200 : forming a dielectric layer 200 having a first trench 210 on a substrate 100 .
[0056] Specifically, Figure 3 is a cross-sectional schematic diagram of the semiconductor structure after step S200, referring to Figure 3 In this embodiment, the first groove 210 exposes a portion of the first conductive layer 110 in a direction perpendicular to the substrate 100, so that a conductive material in contact with the first conductive layer 110 is formed in a subsequent step, thereby realizing the transmission of signals in the first conductive layer 110. For example, a dielectric layer 200 may be first formed on the surface of the substrate 100, and then the dielectric layer 200 may be etched to form the first groove 210; or a sacrificial layer matching the position and size of the first groove 210 may be first formed on the surface of the substrate 100, and then the dielectric layer 200 is formed in the gap of the sacrificial layer, and finally the sacrificial layer is removed by cleaning to form the first groove 210.
[0057] Further, the thickness of the dielectric layer 200 is 100nm to 1500nm, for example, 500nm, 1000nm, etc. The specific thickness of the dielectric layer 200 is determined by the height of the second conductive layer 600 to be formed. The dielectric layer 200 can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The material of the dielectric layer 200 can be a low-K (dielectric constant) material, for example, at least one of silicon dioxide (SiO2), silicon oxycarbide (SiCO) or fluorinated silicon glass (FSG).
[0058] S300 : forming a first filling layer 211 that partially fills the first trench 210 .
[0059] Figure 4 is a schematic cross-sectional view of a semiconductor structure after step S300 of an embodiment, referring to Figure 4 In this embodiment, the sidewall of the first filling layer 211 is in contact with the inner wall of the first trench 210, that is, the projection of the first filling layer 211 on the substrate 100 completely covers the exposed substrate 100, or completely covers the exposed first conductive layer 110, and the top of the first filling layer 211 is lower than the top of the dielectric layer 200. It can be understood that in the subsequent etching step to form other trench structures, if the first conductive layer 110 and the dielectric layer 200 are completely exposed to the etching liquid or etching gas, the first conductive layer 110 and the dielectric layer 200 will be damaged. Therefore, in step S300, by making the first filling layer 211 cover the exposed first conductive layer 110 and part of the sidewall of the first trench 210, in the subsequent etching step, it is possible to prevent the first conductive layer 110 in the substrate 100 from being damaged, and to prevent the sidewall of the covered dielectric layer 200 from being etched laterally, thereby improving the reliability of the semiconductor structure.
[0060] S400 : forming a first mask layer 300 having a first opening 310 on the dielectric layer 200 , wherein the first opening 310 exposes the first filling layer 211 and a portion of the dielectric layer 200 .
[0061] Specifically, Figure 5 FIG. 1 is a cross-sectional view of a semiconductor structure after step S400 of an embodiment, referring to FIG. Figure 5In this embodiment, the first opening 310 on the first mask layer 300 exposes the first filling layer 211 and a portion of the dielectric layer 200. The position and size of the first opening 310 correspond to the position and size of the second trench 220 to be formed, so that the second trench 220 is formed based on the first mask layer 300 in the subsequent steps. The first mask layer 300 may be a photoresist layer or a hard mask layer, such as silicon nitride, silicon oxynitride, etc., and the material of the first mask layer 300 may be selected appropriately according to the etching time and the etchant.
[0062] S500 : etching the dielectric layer 200 using the first mask layer 300 as a mask to form a second trench 220 .
[0063] Figure 6 is a schematic cross-sectional view of a semiconductor structure after step S500 of an embodiment, Figure 7 for Figure 6 A schematic top view of a semiconductor structure of an embodiment. To simplify the drawing, Figure 7 Only one second groove 220 and the corresponding first filling layer 211 are shown. Figure 6 and Figure 7 In this embodiment, the extension direction of the first trench 210, the extension direction of the first filling layer 211 and the extension direction of the second trench 220 are all the same, and the symmetry axis of the first trench 210 parallel to the extension direction coincides with the symmetry axis of the second trench 220 parallel to the extension direction, thereby ensuring the etching effect of the second trench 220. Further, after step S500, the following step may be included: removing the first mask layer 300 on the surface of the substrate 100.
[0064] In other embodiments, the cross-section of the first trench 210 and the first filling layer 211 in a direction parallel to the surface of the substrate 100 is circular or square, and a conductor is subsequently filled in the first trench 210 to form a conductive plug, and the cross-section of the second trench 220 in a direction parallel to the surface of the substrate 100 is linear, and a conductor is subsequently filled in the second trench 220 to form a conductive line.
[0065] The width of the second groove 220 is greater than the width of the first groove 210. The width of the groove refers to the dimension of the groove in the direction parallel to the substrate 100 and perpendicular to the symmetry axis of the groove. Specifically, it can be understood that the width of the first filling layer 211 is the same as the width of the first groove 210. Figure 7 The width of the first trench 210 is d1, and the width of the second trench 220 is d2. By setting the width of the second trench 220 to be greater than the width of the first trench 210 in step S500, the target structure of the second conductive layer 600 can be formed in subsequent steps.
[0066] S600: removing the first filling layer 211 .
[0067] Figure 8 FIG. 1 is a cross-sectional view of a semiconductor structure after step S700 of an embodiment, referring to FIG. Figure 8 In the present embodiment, the remaining first filling layer 211 in the first trench 210 and the second trench 220 is completely removed, thereby completely exposing the sidewalls of the dielectric layer 200 and the top of the first conductive layer 110, so that conductive material can be filled in the first trench 210 and the second trench 220 in subsequent steps.
[0068] Furthermore, the first filling layer 211 in the first groove 210 and the second groove 220 can be completely removed by wet etching. Moreover, by selecting the first filling layer 211 and the dielectric layer 200 with a larger etching selectivity, for example, the etching selectivity of the dielectric layer 200 to the first filling layer 211 can be made greater than 7, for example, the etching selectivity can be made 8, so as to reduce damage to the dielectric layer 200 during the wet etching process, thereby avoiding the residual dielectric layer 200 from being too thin, and further preventing the second conductive layer 600 formed in the adjacent second groove 220 from short-circuiting, thereby improving the reliability of the semiconductor structure.
[0069] S700 : forming a conductive material in the first trench 210 and the second trench 220 .
[0070] Fig. 9 FIG. 1 is a cross-sectional view of a semiconductor structure after step S800 of an embodiment, referring to FIG. Fig. 9 In this embodiment, the first trench 210 and the second trench 220 are completely filled with conductive material, and the conductive materials in the first trench 210 and the second trench 220 together constitute the second conductive layer 600, that is, the bottom of the second conductive layer 600 is in contact with the top of the first conductive layer 110 in the substrate 100, the sidewall of the second conductive layer 600 is arranged in contact with the sidewall of the dielectric layer 200, and the top of the second conductive layer 600 extends upward to be flush with the top of the dielectric layer 200 or higher than the top of the dielectric layer 200. Further, the conductive material can be a metal material, such as copper, aluminum, etc.
[0071] In other embodiments, before forming the second conductive layer 600 , a barrier layer such as titanium nitride, tantalum nitride, etc. is formed on the sidewall surface of the dielectric layer 200 to prevent the material of the second conductive layer 600 from diffusing into the dielectric layer 200 .
[0072] In this embodiment, the method for forming a semiconductor structure includes: providing a substrate 100; forming a dielectric layer 200 having a first trench 210 on the substrate 100; forming a first filling layer 211 partially filling the first trench 210; forming a first mask layer 300 having a first opening 310 on the dielectric layer 200, the first opening 310 exposing the first filling layer 211 and a portion of the dielectric layer 200; etching the dielectric layer 200 using the first mask layer 300 as a mask to form a second trench 220; removing the first filling layer 211; and forming a conductive material in the first trench 210 and the second trench 220. In this embodiment, by first forming the first trench 210, partially filling the first filling layer 211 in the first trench 210, and then removing the first filling layer 211 after forming the second trench 220, the height of the first filling layer 211 can be matched with the arrangement density of the semiconductor structure, thereby avoiding excessive lateral etching of the dielectric layer 200 by the etching process, avoiding the short circuit phenomenon of the conductive material, and improving the electrical performance of the semiconductor structure. Moreover, in this embodiment, the second trench 220 having a larger width than the first trench 210 is formed by an etching process, so that the first trench 210 and the second trench 220 can be used together to deposit conductive materials to form a semiconductor structure with better contact performance and structural reliability.
[0073] In one embodiment, before step S200, the process further includes: forming a first barrier layer 400 on the substrate 100. Figure 3 If a first barrier layer 400 is formed on the surface of the substrate 100, the dielectric layer 200 is formed on the first barrier layer 400. The material of the first barrier layer 400 is silicide, such as at least one of silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon carbon nitride oxide (SiCNO). In this embodiment, the first barrier layer 400 can prevent the mutual diffusion of the first conductive layer 110 and the dielectric layer 200 to avoid the degradation of the electrical performance of the semiconductor structure, and the first barrier layer 400 can also protect the substrate 100, thereby preventing the first conductive layer 110 in the substrate 100 from being damaged during the subsequent etching process.
[0074] In one embodiment, continue to refer to Figure 3, step S200 also includes: forming a second barrier layer 500 on the dielectric layer 200. The second barrier layer 500 can protect the dielectric layer 200 in the subsequent etching process to prevent the top of the dielectric layer 200 from being damaged, thereby improving the performance of the semiconductor structure. Among them, the material of the second barrier layer 500 can be the same as or different from the material of the first barrier layer 400, which is not specifically limited in this embodiment. Further, the first barrier layer 400, the dielectric layer 200 and the second barrier layer 500 can be formed in sequence on the surface of the substrate 100, and the second barrier layer 500, the dielectric layer 200 and the first barrier layer 400 can be etched in sequence through a one-step etching process until the surface of the substrate 100, thereby simplifying the process flow.
[0075] Fig.10 FIG. 1 is a flow chart of a method for forming a semiconductor structure according to another embodiment. Fig.10 In this embodiment, step S300 includes steps S310 to S320.
[0076] S310 : forming an initial first filling layer 212 in the first trench 210 and on the dielectric layer 200 .
[0077] Fig.11 is a schematic cross-sectional view of a semiconductor structure after step S310 of an embodiment, referring to Fig.11 In this embodiment, the top of the initial first filling layer 212 is higher than the second barrier layer 500. Further, the initial first filling layer 212 can be formed by chemical vapor deposition or physical vapor deposition, and after the initial first filling layer 212 is formed, the top of the initial first filling layer 212 is processed by chemical mechanical planarization (CMP) to more accurately perform target depth etching in subsequent steps, thereby improving the process yield of the semiconductor structure.
[0078] S320: Etch back the entire initial first filling layer 212 on the dielectric layer 200 and part of the initial first filling layer 212 in the first trench 210, and the remaining initial first filling layer 212 serves as the first filling layer 211. It can be understood that if the overall height of the first barrier layer 400, the dielectric layer 200 and the second barrier layer 500 is H1, and the height of the initial first filling layer 212 on the surface of the second barrier layer 500 is H2, then the etching back depth is H3, and the first filling layer 211 with a target height H4 can be formed in the first trench 210, wherein H4=H1+H2-H3, and the height and depth both refer to the dimensions in the direction perpendicular to the substrate 100. In this embodiment, the semiconductor structure shown in the figure can be formed by etching back in step S320.
[0079] In one embodiment, step S320 etches back the entire initial first filling layer 212 on the dielectric layer 200 and a portion of the initial first filling layer 212 in the first groove 210, and the remaining initial first filling layer 212 serves as the first filling layer 211, including: etching back the entire initial first filling layer 212 on the dielectric layer 200 and a portion of the initial first filling layer 212 in the first groove 210 so that the height ratio of the first filling layer 211 satisfies a preset range, and the remaining initial first filling layer 212 serves as the first filling layer 211; wherein the height ratio is the ratio of the height of the first filling layer 211 in a direction perpendicular to the substrate 100 to the depth of the first groove 210.
[0080] Specifically, continue to refer to Figure 4 ,exist Figure 4 In the illustrated embodiment, the height of the first filling layer 211 in a direction perpendicular to the substrate 100 is H4, the depth of the first trench 210 is H1, and the height ratio is H4 / H1. It is understandable that if the height ratio is too large, that is, the height of the first filling layer 211 is too high, then in the subsequent step of removing the first filling layer 211, the etchant cannot accurately reach the bottom of the first filling layer 211, resulting in the first filling layer 211 not being completely and effectively stripped, thereby resulting in a reduction in the contact area between the second conductive layer 600 and the first conductive layer 110, an increase in contact resistance, and a decrease in the electrical performance of the semiconductor structure. If the height ratio is too small, the etching time is long when the first filling layer 211 is formed by the etching back method, which is easy to cause damage to the top of the dielectric layer 200, thereby causing a short circuit between adjacent second conductive layers 600. Therefore, it is necessary to select an appropriate height ratio to obtain better device performance.
[0081] In one embodiment, the height ratio of the first filling layer 211 is between 0.7 and 0.9, for example, the height ratio of the first filling layer 211 may be 0.8, that is, the ratio of the height of the first filling layer 211 along the direction perpendicular to the substrate 100 to the depth of the first trench 210 is 0.8. With the height ratio range of this embodiment, a better removal effect of the first filling layer 211 can be achieved in step S600 without causing much damage to the top of the dielectric layer 200.
[0082] In one embodiment, step S400 includes steps S410 to S420.
[0083] S410 : forming a first mask layer 300 in the first trench 210 and on the dielectric layer 200 .
[0084] Fig.12 is a cross-sectional schematic diagram of a semiconductor structure after step S410 of an embodiment, referring to Fig.12, the first mask layer 300 covers the top of the first filling layer 211 and completely fills the first trench 210, and the top of the first mask layer 300 is higher than the second barrier layer 500. In one embodiment, the first mask layer 300 is a photoresist layer, and the patterning method of the photoresist layer is relatively simple. In addition, in this embodiment, the first mask layer 300 is used as a mask for etching with fewer steps, that is, the first mask layer 300 using the photoresist layer can withstand the etching process without causing damage to the semiconductor structure.
[0085] S420 : removing the entire first mask layer 300 in the first trench 210 and a portion of the first mask layer 300 on the dielectric layer 200 .
[0086] Specifically, taking the first mask layer 300 as a photoresist layer as an example, the first mask layer 300 can be exposed through a photomask, wherein the pattern of the photomask is the same as the projection of the second groove 220 to be formed on the substrate 100, and the photoresist layer is developed after exposure, thereby removing all the first mask layer 300 in the first groove 210 and part of the first hard mask layer on the dielectric layer 200, so as to form a Figure 5 The device structure shown.
[0087] In one embodiment, step S500, etching the dielectric layer 200 with the first mask layer 300 as a mask to form the second trench 220, includes: etching the dielectric layer 200 with the first mask layer 300 as a mask to form the second trench 220, wherein the depth of the second trench 220 is less than the depth of the first trench 210, and the bottom of the second trench 220 is lower than the top of the first filling layer 211. When the bottom of the second trench 220 is lower than the top of the first filling layer 211, in the process of forming the second trench 220, the height of the first filling layer 211 can regulate the etching rate of the second trench 220. Specifically, the first filling layer 211 occupies the opening space of the first trench 210, so that the number of etching ions entering the first trench 210 is reduced, thereby reducing the lateral etching rate of the second trench 220, reducing the size of the second trench 220 along the substrate surface direction, and preventing adjacent second trenches 220 from being connected.
[0088] In one embodiment, the ratio of the depth of the second trench 220 to the depth of the first trench 210 is between 0.5 and 0.8, that is, the ratio of the depth of the second trench 220 to the depth of the first trench 210 can be, for example, 0.5, 0.7, etc. Wherein, when the second barrier layer 500 is formed, the depth of the first trench 210 refers to the vertical distance between the top of the second barrier layer 500 and the surface of the substrate 100, and the depth of the second trench 220 refers to the vertical distance between the top of the second barrier layer 500 and the bottom of the second trench 220. Figure 8It can be understood that, since the width of the second groove 220 is greater than the width of the first groove 210, when the conductive material contacts the dielectric layer 200 region corresponding to the second groove 220, the contact area is greater than the area when the conductive material contacts the dielectric layer 200 region corresponding to the first groove 210. The larger the contact area, the stronger the corresponding adhesion and stability. If the depth of the second groove 220 is too large, the first conductive layer 110 in the substrate 100 will be exposed, thereby affecting the device performance. Therefore, in this embodiment, by setting the ratio of the depth of the second groove 220 to the depth of the first groove 210 to be between 0.5 and 0.8, the connection strength between the conductive material and the dielectric layer 200 can be improved without affecting the device performance, thereby improving the reliability of the semiconductor structure.
[0089] In one embodiment, the substrate 100 includes a first region 130 and a second region 140, the first trenches 210 and the second trenches 220 are both located in the first region 130 and the second region 140, and the density of the first trenches 210 in the first region 130 is greater than the density of the first trenches 210 in the second region 140. Specifically, Fig.13 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure including a first region 130 and a second region 140 according to an embodiment of the present invention. Fig.13 In this embodiment, the first area 130 is a region where components and wirings are densely distributed, and the second area 140 is a region where components and wirings are sparsely distributed. It should be noted that the first area 130 and the second area 140 are divided only by distribution density. In this embodiment, by making the density of the first trenches 210 in the first area 130 greater than the density of the first trenches 210 in the second area 140, the layout of the device structure can be better matched, thereby obtaining a higher degree of device integration.
[0090] In one embodiment, the height ratio of the first filling layer 211 in the first area 130 is greater than the height ratio of the first filling layer 211 in the second area 140. Specifically, the depths of the first trench 210 in the first area 130 and the first trench 210 in the second area 140 are the same, and by adjusting the height of the first filling layer 211 in the first area 130 to be greater than that in the second area 140, the lateral etching rate of the second trench 220 in the first area 130 is less than the lateral etching rate of the second trench 220 in the second area 140, ensuring that the conductive material subsequently formed in the first area 130 will not short-circuit.
[0091] In one embodiment, the depth of the second trench 220 in the second region 140 is equal to the depth of the second trench 220 in the first region 130, so that the electrical properties of the conductive material formed in the second region 140 and the conductive material formed in the first region 130 are the same, thereby improving the electrical performance of the semiconductor device. Preferably, the width of the second trench 220 in the second region 140 is equal to the width of the second trench 220 in the first region 130, and the width is the size of the second trench 220 along the surface direction of the substrate 100.
[0092] In one embodiment, the depth of the second trench 220 in the second region 140 is greater than the depth of the second trench 220 in the first region 130 . Fig.14 is a cross-sectional schematic diagram of a semiconductor structure of the prior art, referring to Fig.14 It is understandable that, in the first region 130, due to the higher density of the structure arrangement, it is more likely to cause the lateral etching problem of the dielectric layer 200, and further cause the short circuit phenomenon of the second conductive layer 600. Fig.13 In this embodiment, by setting the depth of the second trench 220 in the second zone 140 to be greater than the depth of the second trench 220 in the first zone 130, the connection strength of the conductive material in the second zone 140 can be ensured, and the short circuit phenomenon of the conductive material in the first zone 130 can be avoided, thereby providing a semiconductor structure with better performance.
[0093] A semiconductor structure is formed by using the semiconductor structure forming method as described above, referring to Fig. 9 The semiconductor structure includes: a substrate 100; a dielectric layer 200 disposed on the substrate 100, wherein the dielectric layer 200 has a first trench 210 and a second trench 220, wherein the second trench 220 exposes the first trench 210 in a vertical direction; and a second conductive layer 600, which is made of a conductive material and is disposed in the first trench 210 and the second trench 220. The semiconductor structure can be provided with a second trench 220 having a larger width than the first trench 210, so that the first trench 210 and the second trench 220 can be used together for depositing conductive material, so as to form a second conductive layer 600 with better contact performance and structural reliability.
[0094] It should be understood that although Figure 1 and Fig.10 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 and Fig.10At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0095] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0096] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a dielectric layer having a plurality of first trenches on the first region and the second region of the substrate, wherein a density of the first trenches in the first region is greater than a density of the first trenches in the second region, and a depth of the first trenches in the first region is the same as a depth of the first trenches in the second region; forming a first filling layer partially filling each of the first trenches, wherein a height of the first filling layer in the first region is greater than a height of the first filling layer in the second region; forming a first mask layer having a first opening on the dielectric layer, wherein the first opening exposes the first filling layer and a portion of the dielectric layer; Using the first mask layer as a mask, etching the dielectric layer to form a plurality of second trenches located on the first region and the second region; removing the first filling layer; A conductive material is formed in the first trench and the second trench.
2. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a first filling layer in each of the first trenches comprises: forming an initial first filling layer in each of the first trenches and on the dielectric layer; All of the initial first filling layer on the dielectric layer and part of the initial first filling layer in the first groove are etched back, and the remaining initial first filling layer serves as the first filling layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: The step of etching back all of the initial first filling layer on the dielectric layer and a portion of the initial first filling layer in the first groove, with the remaining initial first filling layer serving as the first filling layer, comprises: Back-etching all of the initial first filling layer on the dielectric layer and part of the initial first filling layer in the first groove so that the height ratio of the first filling layer meets a preset range, and the remaining initial first filling layer serves as the first filling layer; The height ratio is the ratio of the height of the first filling layer along a direction perpendicular to the substrate to the depth of the first groove.
4. The method for forming a semiconductor structure according to claim 3, characterized in that: The height ratio of the first filling layer is between 0.7 and 0.
9.
5. The method for forming a semiconductor structure according to claim 4, characterized in that: A ratio of the depth of the second trench to the depth of the first trench is between 0.5 and 0.
8.
6. The method for forming a semiconductor structure according to claim 1, wherein: A depth of the second trench in the second region is greater than a depth of the second trench in the first region.
7. The method for forming a semiconductor structure according to claim 2, wherein: An etching selectivity ratio between the dielectric layer and the first filling layer is greater than 7.
8. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first mask layer having a first opening on the dielectric layer, wherein the first opening exposes the first filling layer and a portion of the dielectric layer, comprises: forming the first mask layer in each of the first trenches and on the dielectric layer; The entire first mask layer in the first trench and a portion of the first mask layer on the dielectric layer are removed.
9. The method for forming a semiconductor structure according to claim 8, characterized in that: The first mask layer is a photoresist layer.
10. The method for forming a semiconductor structure according to claim 1, wherein: The etching of the dielectric layer using the first mask layer as a mask to form a plurality of second trenches located on the first region and the second region comprises: The dielectric layer is etched using the first mask layer as a mask to form the second trench, wherein the depth of the second trench is less than the depth of the first trench, and the bottom of the second trench is lower than the top of the first filling layer.
11. The method for forming a semiconductor structure according to claim 1, wherein: A depth of the second trench in the second region is equal to a depth of the second trench in the first region.
12. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 11.
Citation Information
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