Silicon wafer processing method and device

Abstract

The embodiment of the present application provides a silicon wafer processing method and device. The silicon wafer processing method includes: polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer; providing a reaction gas, wherein the reaction gas includes at least oxygen and a halogen-containing gas; at a first preset temperature, using the oxygen and the halogen-containing gas to react with the surface of the silicon wafer to form a micro-suede surface on the surface of the silicon wafer, and removing metal impurities from the silicon wafer. The embodiment of the present application can reduce the consumption of chemicals and water resources, reduce the impact of the silicon wafer micro-suede manufacturing process on the environment, avoid damage to the silicon wafer and its micro-suede, and is also conducive to the formation of a microstructure with higher coverage and higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, the metal impurities on the surface of the silicon wafer can also be removed, thereby improving the purity of the silicon wafer.

Description

Technical Field

[0001] The present application belongs to the field of photovoltaic technology, and specifically relates to a silicon wafer processing method and device. Background Art

[0002] In recent years, by reducing the cost of photovoltaic power generation and increasing the proportion of photovoltaic power generation, the goal of carbon neutrality can be achieved and the proportion of clean energy connected to the grid can be increased. Improving the conversion efficiency of solar cells can reduce the cost of solar cells, reduce the scale of power stations, land costs and construction costs, and thus reduce the cost of photovoltaic power generation. In specific applications, by making a micro-suede surface on the silicon wafer of a solar cell, the optical loss of the solar cell can be effectively reduced to improve the conversion efficiency of the solar cell.

[0003] In the existing technology, reactive ion etching or laser etching is usually used to prepare the micro-texture on the surface of silicon wafers. However, when the above process is used to prepare the micro-texture on the surface of silicon wafers, not only is the process complicated, but it also consumes a lot of chemicals and water, has a great impact on the environment, and the quality of the micro-texture of the silicon wafer is poor, and the light trapping effect is limited. In addition, the metal impurities in the existing silicon wafers affect the minority carrier lifetime, which will limit the improvement of the photoelectric conversion efficiency of solar cells. Summary of the invention

[0004] The present application aims to provide a silicon wafer processing method and device to solve the problem that the existing silicon wafer processing method consumes a lot of chemicals and water, has a great impact on the environment, and has poor micro-texture quality of the silicon wafer.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, the present application discloses a silicon wafer processing method, the silicon wafer processing method comprising:

[0007] Polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer;

[0008] Providing a reaction gas, wherein the reaction gas comprises at least oxygen and a halogen-containing gas;

[0009] At a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities on the silicon wafer.

[0010] Optionally, the step of polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer includes:

[0011] The silicon wafer is chemically polished using an acidic solution or an alkaline solution to remove a damaged layer on the surface of the silicon wafer; wherein the acidic solution includes at least one of a hydrofluoric acid solution and a nitric acid solution, and the alkaline solution includes at least one of a potassium hydroxide solution and a sodium hydroxide solution.

[0012] Optionally, after the oxygen and the halogen-containing gas are reacted with the surface of the silicon wafer at the first preset temperature to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities on the silicon wafer, the method further comprises:

[0013] After a preset time, the silicon wafer is cooled by using an inert gas to a temperature below a second preset temperature; wherein the second preset temperature is lower than the first preset temperature.

[0014] Optionally, the first preset temperature is 700°C-1300°C, and the second preset temperature is 200°C.

[0015] Optionally, the step of using the oxygen and the halogen-containing gas to react with the surface of the silicon wafer at the first preset temperature to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities on the surface of the silicon wafer includes:

[0016] At a first preset temperature, the oxygen is reacted with the surface of the silicon wafer to obtain silicon dioxide, and the halogen-containing gas is reacted with the silicon, silicon dioxide and metal impurities on the surface of the silicon wafer. The difference in reaction rate between the halogen-containing gas and the silicon and silicon dioxide is utilized to form a micron-scale micro-texture surface on the surface of the silicon wafer, and the metal impurities on the surface of the silicon wafer are removed.

[0017] Optionally, the halogen-containing gas includes at least one of chlorine, bromine, fluorine, carbon tetrachloride, hydrogen chloride, and freon;

[0018] The inert gas includes at least one of nitrogen, argon and helium.

[0019] In a second aspect, the present application further discloses a silicon wafer processing device, which includes: a carrier, a conveying mechanism, a processing chamber, and an air intake mechanism; wherein:

[0020] The processing chamber is fixedly connected to the carrier, and an opening is provided on the processing chamber;

[0021] The conveying mechanism is slidably connected to the carrier and is opposite to the opening. The conveying mechanism is used to transport a plurality of silicon wafers into the processing chamber through the opening, or to output the plurality of silicon wafers from the processing chamber. When the silicon wafers are polished to remove a damaged layer on the surface of the silicon wafers, the conveying mechanism can drive the plurality of silicon wafers into the processing chamber.

[0022] A heating mechanism is provided in the processing chamber, and the heating mechanism is used to adjust the temperature in the processing chamber;

[0023] The processing chamber is also provided with an air inlet, and the air inlet mechanism is connected to the air inlet; the air inlet mechanism can introduce reaction gas into the processing chamber, and the reaction gas includes at least oxygen and halogen-containing gas, so that the oxygen and the halogen-containing gas react with the surface of the silicon wafer at a first preset temperature, forming a micro-suede surface on the surface of the silicon wafer, and removing metal impurities from the silicon wafer.

[0024] Optionally, the silicon wafer processing device further comprises a gate for sealing the opening, and the gate is movably connected to the opening.

[0025] Optionally, the carrier includes a first connection portion for fixedly connecting to the processing chamber and a second connection portion for slidably connecting to the conveying mechanism, and the conveying mechanism includes a sealing portion for sealing the opening and a load-bearing portion for placing the plurality of silicon wafers;

[0026] The sealing portion is slidably connected to the second connecting portion, and the sealing portion is opposite to the opening;

[0027] The load-bearing part is connected to a side of the sealing part close to the processing chamber.

[0028] Optionally, the load-bearing part comprises a supporting structure and a carrying plate for placing the plurality of silicon wafers, the supporting structure is connected to a side of the sealing part close to the processing chamber, and the carrying plate is arranged on the supporting structure;

[0029] The material of the carrier plate includes at least one of quartz, alumina, graphite, carbon-carbon and silicon carbide.

[0030] In the embodiment of the present application, the silicon wafer is polished to remove the damaged layer on the surface of the silicon wafer; then a reaction gas is provided, wherein the reaction gas includes at least oxygen and a halogen-containing gas; at a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-suede surface on the surface of the silicon wafer, and remove the metal impurities on the surface of the silicon wafer. By etching the surface of the silicon wafer with oxygen and halogen-containing gas to obtain a micro-suede surface, it is not only possible to reduce the consumption of chemicals and water resources, but also to reduce the impact of the silicon wafer micro-suede manufacturing process on the environment. Moreover, the use of a gas etching method to prepare a micro-suede surface on the surface of the silicon wafer not only has a small impact on the silicon wafer, but also can avoid damage to the silicon wafer and its micro-suede surface, and is also conducive to forming a microstructure with a higher coverage and a higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, at the first preset temperature, the halogen-containing gas can also react with the metal impurities of the silicon wafer to remove the metal impurities, improve the purity of the silicon wafer, and further improve the photoelectric conversion efficiency of the solar cell using the silicon wafer.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0033] Figure 1 is a flowchart of a silicon wafer processing method according to an embodiment of the present invention;

[0034] Figure 2 This is one of the structural schematic diagrams of a silicon wafer processing device described in an embodiment of the present application;

[0035] Figure 3 It is a schematic diagram of the structure of the micro-texture surface of an existing silicon wafer;

[0036] Figure 4 is a schematic structural diagram of a micro-texture surface of a silicon wafer treated by the treatment method of the present application;

[0037] Figure 5 is a flowchart of another silicon wafer processing method according to an embodiment of the present invention;

[0038] Figure 6 This is the second structural schematic diagram of a silicon wafer processing device described in an embodiment of the present application.

[0039] Figure numerals: 1 - conveying mechanism, 11 - sealing part, 12 - load-bearing part, 121 - supporting structure, 122 - carrying plate, 2 - processing chamber, 21 - opening, 22 - air inlet, 23 - air outlet, 3 - silicon wafer, 31 - microstructure, 4 - carrier, 41 - first connecting part, 42 - second connecting part, 421 - slide rail, 5 - air inlet mechanism, 511 - first pipeline, 512 - second pipeline, 513 - third pipeline, 521 - first valve, 522 - second valve, 523 - third valve. DETAILED DESCRIPTION

[0040] Embodiments of the present invention will be described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0041] The term "first" or "second" in the specification and claims of the present application may include one or more of the features explicitly or implicitly. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0042] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0043] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] Reference Figure 1 , shows a flow chart of steps of a silicon wafer processing method according to an embodiment of the present invention, such as Figure 1 As shown, the silicon wafer processing method may specifically include the following steps:

[0045] Step 101: Polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer.

[0046] In the embodiment of the present application, the damaged layer on the surface of the silicon wafer can be removed by physical polishing or chemical polishing. Specifically, the damaged layer can be cutting residues and impurities on the surface of the silicon wafer. The damaged layer on the surface of the silicon wafer can be removed by polishing, and the roughness of the surface of the silicon wafer can be reduced. This is beneficial to the uniformity of the micro-suede surface formed on the surface of the silicon wafer by gas etching in the subsequent process, and improves the quality of the micro-suede surface on the surface of the silicon wafer.

[0047] In an optional embodiment of the present application, the silicon wafer can be chemically polished using an acidic solution or an alkaline solution to remove a damaged layer on the surface of the silicon wafer; wherein the acidic solution includes at least one of a hydrofluoric acid solution and a nitric acid solution, and the alkaline solution includes at least one of a potassium hydroxide solution and a sodium hydroxide solution.

[0048] Specifically, the temperature of the chemical polishing treatment can be 25 degrees to 100 degrees, and the treatment time can be 5 minutes to 180 minutes. The embodiment of the present application does not specifically limit the temperature and time of the chemical polishing treatment of the silicon wafer.

[0049] Step 102: providing a reaction gas, wherein the reaction gas includes at least oxygen and a halogen-containing gas.

[0050] In the embodiment of the present application, a silicon wafer processing device may be used to perform gas etching on the polished silicon wafer to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities from the silicon wafer.

[0051] Reference Figure 2 , shows a schematic structural diagram of a silicon wafer processing device according to an embodiment of the present application, such as Figure 2 As shown, the silicon wafer processing device may specifically include: a carrier 4, a conveying mechanism 1, a processing chamber 2 and an air intake mechanism 5; wherein the processing chamber 2 is fixedly connected to the carrier 4, and an opening 21 is provided on the processing chamber 2; the conveying mechanism 1 is slidably connected to the carrier 4 and is opposite to the opening 21, and the conveying mechanism 1 can be used to transport multiple silicon wafers 3 into the processing chamber 2 through the opening 21, or to output multiple silicon wafers 3 from the processing chamber 2; a heating mechanism is provided in the processing chamber 2, and the heating mechanism can be used to adjust the temperature in the processing chamber 2.

[0052] In the embodiment of the present application, the conveying mechanism 1 can be used to convey the polished silicon wafer 3 into the processing chamber 2. Specifically, the conveying mechanism 1 can carry more silicon wafers 3 at a time, which can improve the processing efficiency of the silicon wafer 3.

[0053] In practical applications, the opening 21 of the processing chamber 2 may be opened first, so that the conveying mechanism 1 can drive the silicon wafer 3 to pass through the opening 21 and enter the processing chamber 2 .

[0054] In practical applications, the driving mechanism may include a driving structure and a load-bearing structure, and the driving structure may be connected to the load-bearing structure and may be used to drive the load-bearing structure to move. Specifically, the silicon wafer 3 may be manually mounted on the load-bearing structure, and then the driving structure may be controlled to drive the load-bearing structure to move, so that the load-bearing structure may drive the silicon wafer 3 into the processing chamber 2.

[0055] In practical applications, after the conveying mechanism 1 delivers the polished silicon wafer 3 into the processing chamber 2, a gate may be used to seal the opening 21 of the processing chamber 2, thereby sealing the processing chamber 2, so that the processing chamber 2 maintains good sealing performance.

[0056] In the embodiment of the present application, after the conveying mechanism 1 delivers the polished silicon wafer 3 into the processing chamber 2, and after the processing chamber 2 is well sealed, the air intake mechanism 5 can be used to introduce the reaction gas into the processing chamber 2, and the reaction gas includes at least oxygen and halogen-containing gas. Among them, both the oxygen and the halogen-containing gas can react with the silicon on the surface of the silicon wafer 3 to form a micro-suede surface on the surface of the silicon wafer 3. In addition, the halogen-containing gas can also react with the metal impurities on the surface of the silicon wafer 3 to generate easily volatile compounds, so as to separate the metal impurities from the silicon wafer 3 and improve the purity of the silicon wafer 3.

[0057] Optionally, the reaction gas may also include an inert gas. Since the inert gas does not react with the silicon wafer 3 even at high temperatures, by adding the inert gas to the reaction gas, the proportion of halogen-containing gas and oxygen in the reaction gas can be diluted by the inert gas, thereby achieving the purpose of saving halogen-containing gas and oxygen.

[0058] Optionally, the halogen-containing gas may include but is not limited to at least one of chlorine, bromine, fluorine, carbon tetrachloride, hydrogen chloride, and freon. The inert gas may include but is not limited to at least one of nitrogen, argon, and helium. The specific composition of the halogen-containing gas and the inert gas may not be limited in the embodiment of the present application.

[0059] Step 103: At a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities on the silicon wafer.

[0060] In the embodiment of the present application, after the conveying mechanism 1 delivers the polished silicon wafer 3 into the processing chamber 2, and after the processing chamber 2 is well sealed, the heating mechanism can be used to adjust the temperature in the processing chamber 2 to a first preset temperature, so that the oxygen and the halogen-containing gas react with the surface of the silicon wafer 3, forming a micron-level micro-suede surface on the surface of the silicon wafer 3 to reduce the optical loss of the solar cell. Moreover, at the first preset temperature, the halogen-containing gas can react with the metal impurities diffused to the surface of the silicon wafer 3 to generate a compound, and the compound has a low boiling point at the first preset temperature and is easy to volatilize, so that the metal impurities can be separated from the silicon wafer 3, thereby improving the purity of the silicon wafer 3. In actual applications, under high temperature environment, after the halogen-containing gas reacts with the metal impurities on the surface of the silicon wafer 3, the concentration of the metal impurities in the matrix of the silicon wafer 3 is relatively high, and it is easy to diffuse from the matrix of the silicon wafer 3 to the surface of the silicon wafer 3, and react with the halogen-containing gas on the surface of the silicon wafer 3, continuously separating the metal impurities in the matrix of the silicon wafer 3, thereby achieving the effect of purifying the silicon wafer 3, thereby improving the photoelectric conversion efficiency of the solar cell using the silicon wafer 3.

[0061] In practical applications, by using oxygen and halogen-containing gas to etch the surface of the silicon wafer 3 to obtain a micro-suede surface, compared with the method of using chemical solution for liquid etching, it can not only reduce the consumption of chemicals and water resources, but also reduce the impact of the silicon wafer micro-suede manufacturing process on the environment. Moreover, compared with the large impact caused by liquid etching on the surface of the silicon wafer 3, the micro-suede surface prepared on the surface of the silicon wafer 3 by the gas etching method not only has a smaller impact on the silicon wafer 3, but also can avoid damage to the silicon wafer 3 and its micro-suede surface. In addition, compared with the microstructure formed on the surface of the silicon wafer 3 by liquid etching, since the gas etching is in more complete contact with the surface of the silicon wafer 3, the microstructure formed on the surface of the silicon wafer 3 by the gas etching method is smaller in size and deeper in depth. That is, the microstructure with higher coverage and higher aspect ratio obtained by gas etching can greatly enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface.

[0062] For example, the particle size of the microstructure formed on the surface of the silicon wafer 3 by the oxygen and the halogen-containing gas can be 0.1-0.2 microns, and the depth can reach 0.1-0.2 microns accordingly. The particle size of the microstructure obtained by liquid etching is usually 0.5-0.6 microns, and the depth is only 0.05-0.1 microns. Therefore, compared with the microstructure obtained by liquid etching, the microstructure formed on the surface of the silicon wafer 3 by the oxygen and the halogen-containing gas in the present application has a higher coverage rate, a higher aspect ratio, and a better light trapping effect.

[0063] Optionally, the first preset temperature may be specifically 700° C.-1300° C., and when the temperature in the processing chamber 2 is 700° C.-1300° C., it is beneficial to form the micro-texture surface on the surface of the silicon wafer 3 .

[0064] Specifically, the formation process of the micro-texture surface may include: when the temperature in the processing chamber 2 is adjusted to the first preset temperature by the heating mechanism, the oxygen may react with the surface of the silicon wafer 3 to obtain silicon dioxide, and the silicon dioxide may adhere to the surface of the silicon wafer 3 and continuously grow to form oxide balls attached to the surface of the silicon wafer 3. At the same time, the halogen-containing gas may react with the silicon and silicon dioxide on the surface of the silicon wafer 3, and the reaction rate difference between the halogen-containing gas and the silicon and silicon dioxide is utilized to form a micron-scale micro-texture surface on the surface of the silicon wafer 3, and remove metal impurities of the silicon wafer 3.

[0065] In practical applications, the reaction rate of the halogen-containing gas with the silicon on the surface of the silicon wafer 3 is greater than the reaction rate of the halogen-containing gas with the silicon dioxide. Therefore, the halogen-containing gas will preferentially react with the silicon on the surface of the silicon wafer 3 for etching, and then react with the silicon dioxide on the surface of the silicon wafer 3 for etching. By utilizing the difference in reaction rate between the halogen-containing gas and the silicon and silicon dioxide, a micron-scale micro-texture surface can be formed on the surface of the silicon wafer 3.

[0066] The experimental data show that at the first preset temperature, the reaction rate of the halogen-containing gas with the silicon on the surface of the silicon wafer 3 is about 0.87 μmol / s, and the reaction rate of the halogen-containing gas with the silicon dioxide on the surface of the silicon wafer 3 is about 0.33 μmol / s, and the reaction rate of the halogen-containing gas with the silicon on the surface of the silicon wafer 3 is greater than the reaction rate of the halogen-containing gas with the silicon dioxide. In practical applications, since the reaction rate of the halogen-containing gas with the silicon on the surface of the silicon wafer 3 is relatively fast, a microstructure with a deep depth and a high and fine shape can be preferentially formed. Since the reaction rate of the halogen-containing gas with the silicon dioxide on the surface of the silicon wafer 3 is relatively slow, a microstructure with a shallow depth and a short and fat shape can be formed. Through the comprehensive reaction of the halogen-containing gas with the silicon and silicon dioxide on the surface of the silicon wafer 3, the aspect ratio of the microstructure of the micro-suede surface on the surface of the silicon wafer 3 can be made higher, the reflectivity is lower, and the light trapping effect is better.

[0067] In practical applications, at the first preset temperature, the silicon dioxide generated by the reaction of oxygen and silicon will form oxide balls on the surface of the silicon wafer 3. The halogen-containing gas reacts with the silicon and silicon dioxide on the surface of the silicon wafer 3 to form silicon halogen compounds, which can volatilize at the first preset temperature. For example, when the halogen-containing gas is chlorine, at the first preset temperature, the chlorine reacts with the silicon or silicon dioxide on the surface of the silicon wafer 3 to generate silicon tetrachloride that can volatilize.

[0068] It should be noted that after the reaction gas containing at least oxygen and halogen-containing gas is introduced into the reaction chamber 2, the reaction of the oxygen with the silicon and metal impurities on the surface of the silicon wafer 3, and the reaction of the halogen-containing gas with the silicon and silicon dioxide on the surface of the silicon wafer 3 can be carried out simultaneously. Moreover, since the etching depth of the halogen-containing gas is deeper when reacting with the silicon on the surface of the silicon wafer 3, and is shallower when reacting with the silicon dioxide on the surface of the silicon wafer 3, the etching degree of the halogen-containing gas at the shallower position of the silicon wafer surface can be greater than that at the deeper position, thereby forming the following structure: Figure 4 The microstructure shown.

[0069] In some optional embodiments of the present application, in order to form a microstructure with a suitable aspect ratio and reflectivity on the surface of the silicon wafer 3, the oxygen gas introduced in the reaction gas may be 0.05-0.2 L / min, and the halogen-containing gas may be 0.1-99.9 L / min. Figure 3 , showing a schematic diagram of the structure of the micro-texture surface of an existing silicon wafer, referring to Figure 4 , shows a schematic structural diagram of a micro-texture surface of a silicon wafer treated by the treatment method of the present application. Figure 3 , Figure 4 As shown, the micro-texture surface of the silicon wafer 3 may include a plurality of pyramid-shaped microstructures 31. Figure 3 For example, the microstructure 31 of the existing silicon wafer surface is shown in FIG. Figure 4 The microstructure 31 of the silicon wafer 31 shown in the figure has a smaller width and a larger aspect ratio, so that Figure 4 The microstructure 31 of the silicon wafer shown is relatively Figure 3 The reflectivity of the shown microstructure 31 is also lower.

[0070] The experimental data show that by processing the silicon wafer using the method described in the embodiment of the present application, the width of the microstructure 31 of the micro-texture surface of the silicon wafer can be reduced from Figure 3 The 5.8 micron shown is reduced to 5.3 micron, and the aspect ratio is reduced from Figure 3 The 1.01 improvement shown leads to Figure 4 As shown in 1.05, the reflectivity is given by Figure 3 The 5.8% improvement shown Figure 4 The 4.2% shown greatly improves the light-trapping effect of the micro-suede surface.

[0071] It should be noted that, in actual applications, the heating mechanism can be used to first adjust the temperature in the processing chamber 2 to the first preset temperature, and then the air intake mechanism 5 can be used to input the reaction gas into the processing chamber 2; or the air intake mechanism 5 can be used to first input the reaction gas into the processing chamber 2, and then the heating mechanism can be used to adjust the temperature in the processing chamber 2 to the preset temperature. The embodiments of the present invention do not make specific limitations on this.

[0072] In practical applications, after the micro-texture is formed on the surface of the silicon wafer 3 , the conveying mechanism 1 can be used to take the silicon wafer 3 with the micro-texture formed thereon out of the processing chamber 2 .

[0073] In summary, the silicon wafer processing method described in the embodiment of the present application can at least include the following advantages:

[0074] In the embodiment of the present application, the silicon wafer is polished to remove the damaged layer on the surface of the silicon wafer; then a reaction gas is provided, wherein the reaction gas includes at least oxygen and a halogen-containing gas; at a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-suede surface on the surface of the silicon wafer, and remove the metal impurities of the silicon wafer. By etching the surface of the silicon wafer with oxygen and halogen-containing gas to obtain a micro-suede surface, it is not only possible to reduce the consumption of chemicals and water resources, but also to reduce the impact of the silicon wafer micro-suede manufacturing process on the environment. Moreover, the use of a gas etching method to prepare a micro-suede surface on the surface of the silicon wafer not only has a small impact on the silicon wafer, but also can avoid damage to the silicon wafer and its micro-suede surface, and is also conducive to forming a microstructure with a higher coverage and a higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, at the first preset temperature, the halogen-containing gas can also react with the metal impurities on the surface of the silicon wafer to remove the metal impurities, improve the purity of the silicon wafer, and further improve the photoelectric conversion efficiency of the solar cell using the silicon wafer.

[0075] Reference Figure 5 , shows a flow chart of steps of another silicon wafer processing method according to an embodiment of the present invention, such as Figure 5 As shown, the silicon wafer processing method may specifically include the following steps:

[0076] Step 301: Polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer.

[0077] Specifically, the specific implementation process of this step can refer to step 101 and will not be described in detail here.

[0078] Step 302: providing a reaction gas, wherein the reaction gas includes at least oxygen and a halogen-containing gas.

[0079] Specifically, the specific implementation process of this step can refer to step 102 and will not be described in detail here.

[0080] In the embodiment of the present application, after the conveying mechanism 1 delivers the polished silicon wafer 3 into the processing chamber 2 and the processing chamber 2 is well sealed, the air intake mechanism 5 can be used to input an inert gas into the processing chamber 2 to use the inert gas to replace the air in the processing chamber 2 to avoid air interference with the processing of the silicon wafer 3.

[0081] Specifically, the processing chamber 2 may be evacuated through the gas outlet 23 first, and then the inert gas may be introduced into the processing chamber 2 using the gas inlet mechanism 5 , thereby replacing the air in the processing chamber 2 with the inert gas.

[0082] Step 303: At a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities on the silicon wafer.

[0083] Specifically, the specific implementation process of this step can refer to step 103 and will not be described in detail here.

[0084] Step 304: After a preset time, cool the silicon wafer using an inert gas at a temperature below a second preset temperature; wherein the second preset temperature is lower than the first preset temperature.

[0085] In the embodiment of the present application, after the oxygen and the halogen-containing gas in the reaction gas react with the silicon wafer 3 for a preset time, it can be considered that the oxygen and the halogen-containing gas have fully reacted with the surface of the silicon wafer 3. At this time, the inert gas can be introduced into the processing chamber 2 by using the air intake mechanism 5, and the reaction gas in the processing chamber 2 is replaced by the inert gas, and the temperature in the processing chamber 2 is adjusted to below the second preset temperature to cool the silicon wafer 3, so as to avoid the silicon wafer 3 being in the temperature space for defect formation (belonging to the first preset temperature range, such as 700°C-1050°C) for a long time and forming too many defects. In this way, after the reaction gas reacts with the silicon wafer 3 for a preset time, the inert gas is used to cool the silicon wafer 3, which is conducive to forming a high-quality micro-suede surface on the surface of the silicon wafer 3 and reducing the defects of the silicon wafer 3, thereby further improving the light trapping effect and quality of the micro-suede surface on the surface of the silicon wafer 3.

[0086] Optionally, the preset time may be 5 minutes to 60 minutes. The second preset temperature is lower than the first preset temperature. For example, the first preset temperature may be 700°C-1300°C, and the second preset temperature may be 200°C.

[0087] In practical applications, after the inert gas replaces the processing gas in the processing chamber 2 and cools the silicon wafer 3 , the silicon wafer 3 with the micro-texture surface formed thereon can be taken out of the processing chamber 2 by using the conveying mechanism 1 .

[0088] In summary, the silicon wafer processing device described in the embodiment of the present application can at least include the following advantages:

[0089] In the embodiment of the present application, the silicon wafer is polished to remove the damaged layer on the surface of the silicon wafer; then a reaction gas is provided, wherein the reaction gas includes at least oxygen and a halogen-containing gas; at a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-suede surface on the surface of the silicon wafer, and remove the metal impurities of the silicon wafer. By etching the surface of the silicon wafer with oxygen and halogen-containing gas to obtain a micro-suede surface, it is not only possible to reduce the consumption of chemicals and water resources, but also to reduce the impact of the silicon wafer micro-suede manufacturing process on the environment. Moreover, the use of a gas etching method to prepare a micro-suede surface on the surface of the silicon wafer not only has a small impact on the silicon wafer, but also can avoid damage to the silicon wafer and its micro-suede surface, and is also conducive to forming a microstructure with a higher coverage and a higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, at the first preset temperature, the halogen-containing gas can also react with the metal impurities on the surface of the silicon wafer to remove the metal impurities, improve the purity of the silicon wafer, and further improve the photoelectric conversion efficiency of the solar cell using the silicon wafer. In addition, in the embodiment of the present application, since the silicon wafer is cooled below the second preset temperature using an inert gas after a preset time, a high-quality micro-suede surface can be formed on the surface of the silicon wafer, thereby reducing the optical loss of the solar cell.

[0090] The present application also provides a method Figure 2 and Figure 6 The silicon wafer processing device shown in the figure can specifically include: a carrier 4, a conveying mechanism 1, a processing chamber 2 and an air intake mechanism 5; wherein the processing chamber 2 is fixedly connected to the carrier 4, and an opening 21 is provided on the processing chamber 2; the conveying mechanism 1 is slidably connected to the carrier 4 and is opposite to the opening 21, and the conveying mechanism 1 is used to transport multiple silicon wafers 3 into the processing chamber 2 through the opening 21, or output multiple silicon wafers 3 from the processing chamber 2, and when the silicon wafer 3 is polished to remove the damaged layer on the surface of the silicon wafer 3, the conveying mechanism 1 can drive the multiple silicon wafers 3 into the processing chamber 2; a heating mechanism is provided in the processing chamber 2, and the heating mechanism can be used to adjust the temperature in the processing chamber 2; the processing chamber 2 is also provided with an air intake 22, and the air intake mechanism 5 is connected to the air intake 22, and the air intake mechanism 5 can introduce a reaction gas into the processing chamber 2, and the reaction gas at least includes oxygen and a halogen-containing gas, so that the oxygen and the halogen-containing gas react with the surface of the silicon wafer 3 at a first preset temperature, form a micro-suede surface on the surface of the silicon wafer 3, and remove metal impurities of the silicon wafer 3.

[0091] In the embodiment of the present application, the silicon wafer 3 is polished to remove the damaged layer on the surface of the silicon wafer 3; then the conveying mechanism 1 is controlled to drive multiple silicon wafers 3 into the processing chamber 2; the reaction gas is introduced into the processing chamber 2 by the air intake mechanism 5, and the reaction gas includes at least oxygen and halogen-containing gas; the temperature in the processing chamber 2 is adjusted to a first preset temperature by the heating mechanism, so that the oxygen and the halogen-containing gas react with the surface of the silicon wafer 3, and a micron-level micro-suede surface can be formed on the surface of the silicon wafer 3 to reduce the optical loss of the solar cell. By etching the surface of the silicon wafer 3 with oxygen and halogen-containing gas to obtain a micro-suede surface, not only can the consumption of chemicals and water resources be reduced, but also the impact of the micro-suede manufacturing process of the silicon wafer 3 on the environment can be reduced. The micro-suede surface is prepared on the surface of the silicon wafer 3 by the gas etching method, which not only has a small impact on the silicon wafer 3, but also can avoid damage to the silicon wafer 3 and its micro-suede surface, and is also conducive to forming a microstructure with higher coverage and higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, at the first preset temperature, the halogen-containing gas can also react with metal impurities on the surface of the silicon wafer 3 to remove the metal impurities, improve the purity of the silicon wafer 3, and further improve the photoelectric conversion efficiency of the solar cell using the silicon wafer 3.

[0092] Specifically, the temperature in the processing chamber 2 can be first adjusted to a first preset temperature using a heating mechanism, and then the reaction gas can be input into the processing chamber 2 using the air intake mechanism 5; or the reaction gas can be first input into the processing chamber 2 using the air intake mechanism 5, and then the temperature in the processing chamber 2 can be adjusted to a preset temperature using a heating mechanism. The embodiment of the present invention does not specifically limit this.

[0093] Optionally, the silicon wafer processing device further comprises a gate for sealing the opening 21 , and the gate is movably connected to the opening 21 .

[0094] In the embodiment of the present invention, the gate can open the opening 21, so that the conveying mechanism 1 can drive the silicon wafer 3 to enter the processing chamber 2 through the opening 21. The gate can seal the processing chamber 2 by sealing the opening 21, thereby preventing the gas in the processing chamber 2 from being replaced with air, reducing the heat loss in the processing chamber 2, and improving the stability and processing efficiency of the silicon wafer 3.

[0095] Specifically, the gate may be electrically controlled or manually controlled, which is not specifically limited in the embodiment of the present invention.

[0096] In some other optional embodiments of the present invention, the carrier 4 may include a first connecting part 41 for fixedly connecting to the processing chamber 2 and a second connecting part 42 for slidably connecting to the conveying mechanism 1, and the conveying mechanism 1 may include a sealing part 11 for sealing the opening 21 and a load-bearing part 12 for placing multiple silicon wafers 3; the sealing part 11 can be slidably connected to the second connecting part 42, and the sealing part 11 can be opposite to the opening 21; the load-bearing part 12 is connected to the side of the sealing part 11 close to the processing chamber 2.

[0097] In the embodiment of the present invention, when the sealing part 11 slides along the second connecting part 42 toward the opening 21, the sealing part 11 can drive the silicon wafer 3 on the load-bearing part 12 to enter the processing chamber 2 through the opening 21, and the sealing part 11 can seal the silicon wafer 3 on the load-bearing part 12 in the processing chamber 2, which can improve the stability of the processing of the silicon wafer 3. When the sealing part 11 slides along the second connecting part 42 away from the opening 21, the sealing part 11 can drive the silicon wafer 3 on the load-bearing part 12 to exit the processing chamber 2 through the opening 21, which improves the convenience of the silicon wafer 3 entering and exiting the processing chamber 2.

[0098] Specifically, Figure 6 As shown, the sealing part 11 seals the opening 21 of the processing chamber 2, and the silicon wafer 3 on the load-bearing part 12 can be sealed in the processing chamber 2. Figure 2 As shown, the sealing portion 11 slides away from the opening 21 and drives the silicon wafer 3 on the load-bearing portion 12 to exit the processing chamber 2 .

[0099] Specifically, the conveying mechanism 1 may include a driving structure, which may be connected to the sealing portion 11 and used to drive the sealing portion 11 to slide along the second connecting portion 42 .

[0100] Optionally, the load-bearing portion 12 may include a support structure 121 and a carrier plate 122 for placing a plurality of silicon wafers 3, the support structure 121 may be connected to a side of the sealing portion 11 close to the processing chamber 2, and the carrier plate 122 may be disposed on the support structure 121; the material of the carrier plate 122 may include at least one of quartz, alumina, graphite, carbon-carbon, and silicon carbide. The present embodiment of the application does not specifically limit the material of the carrier plate 122.

[0101] In an embodiment of the present invention, the carrier plate 122 can be used to place the silicon wafer 3, and the carrier plate 122 can drive the silicon wafer 3 into the processing chamber 2. The material of the carrier plate 122 is selected from one of quartz, alumina, graphite, carbon-carbon and silicon carbide, which can prevent the carrier plate 122 from reacting with the silicon wafer 3 in the processing chamber 2 to generate new impurities, thereby improving the quality of the silicon wafer 3.

[0102] Specifically, the second connecting portion 42 may be provided with a slide rail 421 , and the sealing portion 11 may be slidably connected to the slide rail 421 , so that the sealing portion 11 may drive the supporting rod to enter or exit the processing chamber 2 .

[0103] Optionally, the air intake mechanism 5 may include a first pipeline 511 for inputting inert gas, a second pipeline 512 for inputting oxygen, and a third pipeline 513 for inputting halogen-containing gas; the first pipeline 511, the second pipeline 512, and the third pipeline 513 may all be connected to the air inlet 22; a first valve 521 may be provided in the first pipeline 511, a second valve 522 may be provided in the second pipeline 512, and a third valve 523 may be provided in the third pipeline 513.

[0104] In the embodiment of the present invention, when the first valve 521 is opened, an inert gas can be input into the processing chamber 2 through the first pipeline 511; when the second valve 522 is opened, an oxygen-containing gas can be input into the processing chamber 2 through the second pipeline 512; when the third valve 523 is opened, a reaction gas can be input into the processing chamber 2 through the third pipeline 513.

[0105] Specifically, the first valve 521 may be opened first, and an inert gas may be input into the processing chamber 2 through the first pipeline 511, so as to replace the air in the processing chamber 2 with the inert gas. Then, the second valve 522 may be opened, and oxygen may be input into the processing chamber 2 through the second pipeline 512, and the third valve 523 may be opened, and a halogen-containing gas may be input into the processing chamber 2 through the third pipeline 513, and then the first valve 521, the second valve 522 and the third valve 523 may be closed. Then, the temperature in the processing chamber 2 may be adjusted to the first preset temperature using a heating mechanism, and maintained for 5-120 minutes, so as to form a micro-suede surface on the surface of the silicon wafer 3. Finally, the first valve 521 may be opened again, and an inert gas may be input into the processing chamber 2 through the first pipeline 511, so that the inert gas may replace the reaction gas in the processing chamber 2, and the silicon wafer 3 may be cooled to below the second preset temperature.

[0106] Optionally, the halogen-containing gas may include at least one of chlorine, bromine, fluorine, carbon tetrachloride, hydrogen chloride, and freon. The inert gas may include at least one of nitrogen, argon, and helium.

[0107] In summary, the silicon wafer processing device described in the embodiment of the present application can at least include the following advantages:

[0108] In the embodiment of the present application, the silicon wafer is polished to remove the damaged layer on the surface of the silicon wafer; then a reaction gas is provided, wherein the reaction gas includes at least oxygen and a halogen-containing gas; at a first preset temperature, the oxygen and the halogen-containing gas are used to react with the surface of the silicon wafer to form a micro-suede surface on the surface of the silicon wafer, and remove the metal impurities of the silicon wafer. By etching the surface of the silicon wafer with oxygen and halogen-containing gas to obtain a micro-suede surface, it is not only possible to reduce the consumption of chemicals and water resources, but also to reduce the impact of the silicon wafer micro-suede manufacturing process on the environment. Moreover, the use of a gas etching method to prepare a micro-suede surface on the surface of the silicon wafer not only has a small impact on the silicon wafer, but also can avoid damage to the silicon wafer and its micro-suede surface, and is also conducive to forming a microstructure with a higher coverage and a higher aspect ratio, so as to enhance the light trapping effect of the micro-suede surface and improve the quality of the micro-suede surface. Moreover, at the first preset temperature, the halogen-containing gas can also react with the metal impurities on the surface of the silicon wafer to remove the metal impurities, improve the purity of the silicon wafer, and further improve the photoelectric conversion efficiency of the solar cell using the silicon wafer.

[0109] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0110] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A silicon wafer processing method, characterized in that: The silicon wafer processing method comprises: Polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer; Providing a reaction gas, wherein the reaction gas comprises at least oxygen and a halogen-containing gas; At a first preset temperature, the oxygen is reacted with the surface of the silicon wafer to obtain silicon dioxide, and the halogen-containing gas is reacted with the silicon, silicon dioxide and metal impurities on the surface of the silicon wafer. The difference in reaction rate between the halogen-containing gas and the silicon and silicon dioxide is utilized to form a micron-scale micro-suede surface on the surface of the silicon wafer, and the metal impurities on the surface of the silicon wafer are removed; the first preset temperature is 700°C-1300°C.

2. The silicon wafer processing method according to claim 1, characterized in that: The step of polishing the silicon wafer to remove the damaged layer on the surface of the silicon wafer comprises: The silicon wafer is chemically polished using an acidic solution or an alkaline solution to remove a damaged layer on the surface of the silicon wafer; wherein the acidic solution includes at least one of a hydrofluoric acid solution and a nitric acid solution, and the alkaline solution includes at least one of a potassium hydroxide solution and a sodium hydroxide solution.

3. The silicon wafer processing method according to claim 1, characterized in that: After the oxygen and the halogen-containing gas are reacted with the surface of the silicon wafer at the first preset temperature to form a micro-texture surface on the surface of the silicon wafer and remove metal impurities from the silicon wafer, the method further includes: After a preset time, the silicon wafer is cooled by using an inert gas to a temperature below a second preset temperature; wherein the second preset temperature is lower than the first preset temperature.

4. The silicon wafer processing method according to claim 3, characterized in that: The second preset temperature is 200°C.

5. The silicon wafer processing method according to claim 3, characterized in that: The halogen-containing gas includes at least one of chlorine, bromine, fluorine, carbon tetrachloride, hydrogen chloride, and freon; The inert gas includes at least one of nitrogen, argon and helium.

6. A silicon wafer processing device, characterized in that: The silicon wafer processing device comprises: a carrier, a conveying mechanism, a processing chamber and an air intake mechanism; wherein, The processing chamber is fixedly connected to the carrier, and an opening is provided on the processing chamber; The conveying mechanism is slidably connected to the carrier and is opposite to the opening. The conveying mechanism is used to transport a plurality of silicon wafers into the processing chamber through the opening, or to output the plurality of silicon wafers from the processing chamber. When the silicon wafers are polished to remove a damaged layer on the surface of the silicon wafers, the conveying mechanism can drive the plurality of silicon wafers into the processing chamber. A heating mechanism is provided in the processing chamber, and the heating mechanism is used to adjust the temperature in the processing chamber; The processing chamber is also provided with an air inlet, and the air inlet mechanism is connected to the air inlet; the air inlet mechanism can introduce reaction gas into the processing chamber, and the reaction gas includes at least oxygen and halogen-containing gas; at a first preset temperature, the oxygen is reacted with the surface of the silicon wafer to obtain silicon dioxide, and the halogen-containing gas is reacted with the silicon, silicon dioxide and metal impurities on the surface of the silicon wafer, and the reaction rate difference between the halogen-containing gas and the silicon and silicon dioxide is utilized to form a micron-scale micro-suede surface on the surface of the silicon wafer, and the metal impurities on the surface of the silicon wafer are removed; the first preset temperature is 700°C-1300°C.

7. The silicon wafer processing device according to claim 6, characterized in that: The silicon wafer processing device further comprises a gate for sealing the opening, and the gate is movably connected to the opening.

8. The silicon wafer processing device according to claim 6, characterized in that: The carrier comprises a first connection portion for fixedly connecting to the processing chamber and a second connection portion for slidably connecting to the conveying mechanism, and the conveying mechanism comprises a sealing portion for sealing the opening and a load-bearing portion for placing the plurality of silicon wafers; The sealing portion is slidably connected to the second connecting portion, and the sealing portion is opposite to the opening; The load-bearing part is connected to a side of the sealing part close to the processing chamber.

9. The silicon wafer processing device according to claim 8, characterized in that: The load-bearing part comprises a supporting structure and a carrying plate for placing the plurality of silicon wafers, the supporting structure is connected to a side of the sealing part close to the processing chamber, and the carrying plate is arranged on the supporting structure; The material of the carrier plate includes at least one of quartz, alumina, graphite, carbon-carbon and silicon carbide.

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