Interactive layout planning method and related equipment for chip design

Abstract

The present application provides an interactive layout planning method and related equipment for chip design. The method includes: reading the initial layout planning data of the chip design and displaying it in the main page; determining the hard core group to be processed in the initial layout planning data, wherein the hard core group includes multiple hard cores; automatically aligning the hard core group to be processed in the constraint template according to the automatic regular alignment algorithm, obtaining the hard core group after automatic regular alignment and displaying the hard core group after automatic regular alignment in the first window of the main page; responding to the interactive operation of the target hard core in the hard core group after automatic regular alignment in the first window, adjusting the position of the target hard core according to the interactive operation; outputting the layout planning data based on the hard core group after position adjustment.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an interactive layout planning method for chip design and related equipment. Background Art

[0002] Electronic Design Automation (EDA) refers to a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large-scale integrated circuit (VLSI) chips.

[0003] In the floorplan stage of digital chip physical design, a mixed-place method can be used to solve the floorplan problem. This method places hard macros and standard cells at the same time, reducing the workload of engineers and the time for floorplan design.

[0004] However, the inventors of the present application have discovered that in the related art, the hard cores are not neatly arranged after being mixed and placed, which may lead to various problems. Summary of the invention

[0005] In view of this, the present application proposes an interactive layout planning method for chip design and related equipment to solve or partially solve the above problems.

[0006] In a first aspect, the present application provides an interactive layout planning method for chip design, comprising:

[0007] Reading the initial layout planning data of the chip design and displaying it on the main page;

[0008] Determine a hard core group to be processed in the initial layout planning data, wherein the hard core group includes a plurality of hard cores;

[0009] According to the automatic regular alignment algorithm, the hard core group to be processed is automatically regular aligned in the constraint template to obtain the hard core group after automatic regular alignment and display the hard core group after automatic regular alignment in the first window of the main page;

[0010] In response to an interactive operation on a target hard core in the automatically aligned hard core group in the first window, adjusting a position of the target hard core according to the interactive operation;

[0011] Output layout planning data based on the position-adjusted hard core group.

[0012] In a second aspect of the present application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the program includes instructions for executing the method described in the first aspect.

[0013] According to a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method described in the first aspect.

[0014] In a fourth aspect of the present application, a computer program product is provided, comprising computer program instructions, which, when executed on a computer, cause the computer to execute the method described in the first aspect.

[0015] The interactive layout planning method and related equipment for chip design provided in the present application provide a window for interactive operation of the automatically aligned hard core group after automatically aligning the hard core group, so that the user can further adjust the layout of the hard core group. In this way, the automatic alignment and interactive alignment are combined together, so that the user can more conveniently complete the layout planning of the chip design and improve development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided in an embodiment of the present application is shown.

[0018] Figure 2A A basic structural diagram of an EDA tool according to an embodiment of the present application is shown.

[0019] Figure 2B A schematic diagram showing a basic execution flow of a calculation command of an EDA tool according to an embodiment of the present application is shown.

[0020] Figure 3A A flow chart of an exemplary method provided in an embodiment of the present application is shown.

[0021] Figure 3B A schematic diagram of a sub-process for mixed-size hard core planning according to an embodiment of the present application is shown.

[0022] Figure 3C Another sub-process schematic diagram for mixed-size hard core planning according to an embodiment of the present application is shown.

[0023] Figure 4 A schematic diagram of an exemplary interface according to an embodiment of the present application is shown.

[0024] Figure 5A A schematic diagram of an exemplary hard core initial planning layout according to an embodiment of the present application is shown.

[0025] Figure 5B A schematic diagram of an exemplary hard core group to be matched and its target constraint template according to an embodiment of the present application is shown.

[0026] Figure 5C A schematic diagram of an exemplary constraint template according to an embodiment of the present application is shown.

[0027] Figure 5D A schematic diagram showing a hard core matching result excluding a closed area according to an embodiment of the present application is shown.

[0028] Fig. 6A A schematic diagram of mixed-size hard core segmentation according to an embodiment of the present application is shown.

[0029] Figure 6B A schematic diagram of mixed-size hard core matching according to an embodiment of the present application is shown.

[0030] Figure 6C A schematic diagram of area compression according to an embodiment of the present application is shown.

[0031] Fig. 7A A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0032] Figure 7B A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0033] Figure 7C A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0034] Fig.7D A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0035] Fig. 7E A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0036] Figure 7F A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0037] Figure 7GA schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0038] Figure 7H A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0039] Fig.7I A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0040] Figure 7J A schematic diagram of another exemplary interface according to an embodiment of the present application is shown.

[0041] Figure 7K A schematic diagram of another exemplary interface according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0043] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] Figure 1 The schematic diagram of the structure of a computer device 100 provided in an embodiment of the present application is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the device through the bus 110.

[0045] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0046] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). Figure 1 As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) and data to be processed. The processor 102 may also access the stored program instructions and data, and execute the program instructions to operate the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0047] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0048] The peripheral interface 108 may be configured to connect the computer device 100 to one or more peripheral devices to implement information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0049] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0050] It should be noted that, although the above device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0051] Figure 2A A basic structural diagram of an EDA tool 200 according to an embodiment of the present application is shown.

[0052] like Figure 2A As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown in FIG. 1 is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The simulation tool 200 can include a Tcl command (or a graphic / window interface) module 204, various calculation modules (e.g., a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphic / window interface) module 204.

[0053] The Tcl command module 204 mainly performs the functions of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific contents of the instructions.

[0054] According to different computing tasks, each computing module can be divided into, for example, a Place computing module 206, a Route computing module 208, an Optimization computing module 210, etc. The Place computing module 206 can be used to calculate a reasonable placement position for all components, the Route computing module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization computing module 210 can be used to optimize the placement position and wire connection method between each component. The computing process of these computing modules can be, for example, Figure 1 is performed in the processor 102.

[0055] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information, for example, can be stored in Figure 1 in the memory 104.

[0056] Figure 2B FIG. 3 shows a basic execution flow 300 of a calculation command of an EDA tool 200 according to an embodiment of the present application. Figure 2B As shown, in step 302, the user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses the command and distributes it to the corresponding calculation module (e.g., Place calculation module 206). In step 306, each calculation module performs the specific calculation required by each. During this period, as shown in step 308, each calculation module needs to (high frequency, repeatedly) retrieve data from the database system 212 to perform calculations. After the calculation is completed, as shown in step 310, each calculation module can write the calculation results into the database system 212 and return the calculation results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation results to the user 202 through the command interface or graphical user interface (GUI), and the EDA tool 200 ends the processing process of a calculation command. In step 314, the user can evaluate the calculation results and then determine the next plan.

[0057] Floorplan usually refers to placing hard macros into the design and meeting the subsequent standard cell layout requirements. Broadly speaking, floorplan also includes designing the aspect ratio of the die, placing I / O pads, inserting pure physical cells (Welltap, Endcap), and planning the power and ground network.

[0058] As an optional embodiment, it is possible to use Figure 2B The process shown in the figure is used to complete the initial layout planning, thereby obtaining the initial layout planning data for the chip design. When performing preliminary layout planning, a mixed placement method can be used to complete the layout planning. Mixed placement usually refers to the use of an analytical placer to place hard macros and standard cells at the same time. This method places hard macros and standard cells at the same time, reducing the workload of engineers and layout planning design time.

[0059] However, in many cases, the hard cores are not arranged neatly after mixed placement, which can lead to a variety of problems: First, the power ground wiring is difficult, which can easily cause voltage drop (IR drop) problems; second, it occupies more winding resources; third, it produces many closed areas (dead areas), which can lead to difficulties in timing optimization and winding.

[0060] One solution is to align the hard cores after mixing them, which can solve these problems to a certain extent. Packing usually refers to aligning a group of hard cores in a first direction (for example, horizontal direction) and a second direction (vertical direction), and moving them as a whole to a specified position to complete the splicing or alignment of the groups.

[0061] In the related art, the fully automatic hard-core packing technology greatly changes the result of mixed-place, destroying the global optimization result of mixed-place. Therefore, it cannot meet the requirements from the perspective of power consumption, performance, area, or design convergence.

[0062] In view of this, an embodiment of the present application provides an interactive layout planning method for chip design. After automatically aligning the hard core group, a window for interactive operation of the automatically aligned hard core group is provided, so that the user can further adjust the layout of the hard core group. In this way, the automatic alignment and interactive alignment are combined together, so that the user can more conveniently complete the layout planning of the chip design and improve development efficiency.

[0063] Figure 3A The flowchart of the exemplary method 300 provided in the embodiment of the present application is shown. The method 300 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2A A portion of the functionality of the EDA tool 200. Figure 3A As shown, the method 300 may further include the following steps.

[0064] In step 302, initial layout planning data of the chip design is read and displayed on the main page. The initial layout planning data may be layout planning data obtained after mixed placement.

[0065] Figure 4 A schematic diagram of an exemplary interface 400 according to an embodiment of the present application is shown.

[0066] like Figure 4 As shown, the interface 400 may be an operation interface of an EDA software, and the interface 400 may be displayed on a display screen of a computer device. The interface 400 may specifically include a title bar 402, a menu bar 404, a display (View) area 406 located at the center of the interface 400, and a side (Dock) area 408 located on one side of the display area 406. The display area 406 may be used to display or edit information, for example, to display layout planning data of a chip design. The side area 408 is set on one side of the interface 400 and may be limited to a certain area, such as Figure 4 In the interface 400, both the display area 406 and the side area 408 can display corresponding windows. Figure 4 As shown, a window 4062 may be displayed in the display area 406 , and the read initial layout planning data may be displayed in the window 4062 .

[0067] In step 304, a hard core group to be processed in the initial layout planning data is determined, and the hard core group includes multiple hard cores. Figure 4 In the window 4062 of the interface 400, a region is selected using a mouse, and then multiple hard cores in the region are determined as a hard core group to be processed.

[0068] In step 306, the hard core group to be processed is automatically aligned in the constraint template according to the automatic alignment algorithm to obtain the automatically aligned hard core group and display the automatically aligned hard core group in the first window of the main page.

[0069] Figure 5A A schematic diagram of an exemplary hard core initial planning layout 500 according to an embodiment of the present application is shown.

[0070] For the convenience of the following description, the initial planning layout 500 can be as follows: Figure 5A As shown, it includes the layout planning results obtained after the mixed placement corresponding to the initial layout planning data, and allows the user to select a set of hard cores that need to be regularly aligned.

[0071] like Figure 5AAs shown, assuming that the user uses a mouse to select a group of hard cores in the area 502 for regular alignment, the computer device 100 can determine that the hard core group to be processed is the six hard cores 504 circled in the area 502.

[0072] Next, the computer device 100 may perform regular alignment based on the selected hard core group according to an automatic regular alignment algorithm.

[0073] Figure 3B FIG. 2 shows a schematic diagram of a sub-process for mixed-size hard core planning according to an embodiment of the present application. Figure 3B As shown, step 306 may further include the following steps.

[0074] In step 3062, the cell size is determined according to the hard core size of the hard core group to be processed.

[0075] The method for determining the cell size may be different depending on whether the sizes of the hard cores in the hard core group are the same.

[0076] In some embodiments, when the sizes of the hard cores in the hard core group are the same, step 3062 may further include: in response to determining that the sizes of the hard cores in the hard core group are the same, determining the size of the cell according to the size of the hard core in a first direction (e.g., horizontal direction or x-axis direction) and a second direction (e.g., vertical direction or y-axis direction) and the constraint spacing between the hard cores. For example, the length of the cell on the x-axis is obtained by adding the width of the hard core on the x-axis to the constraint spacing in the x-axis direction; similarly, the length of the cell on the y-axis is obtained by adding the width of the hard core on the y-axis to the constraint spacing in the y-axis direction, thereby obtaining the size of the cell.

[0077] In some embodiments, when the sizes of the hard cores in the hard core group are different, step 3062 may further include: in response to determining that the hard core group has at least two hard cores of different sizes, using an approximate greatest common divisor method to determine the cell size according to the sizes of each hard core in the first direction and the second direction. Specifically, since there are hard cores of different sizes in the hard core group to be processed, the size of the cell needs to be reasonably planned, otherwise it will cause large blank areas in some cells that are not filled by hard cores and form closed areas. In this embodiment, the approximate greatest common divisor method is used to calculate the optimal cell size in the x-axis or y-axis direction, that is, the cell size is determined based on an approximate greatest common divisor, and the degree of approximation can be set as needed.

[0078] In step 3064, the number of rows and columns of the constraint template is determined.

[0079] The number of rows and columns of the constraint template may be specified by the user, for example, by inputting the number of rows and columns in the interface where the layout 500 is located to obtain the number of rows and columns of the constraint template.

[0080] In some embodiments, when the user does not specify the number of rows and columns of the constraint template, the number of rows and columns of the constraint template can be automatically calculated. Figure 5B As shown, the minimum rectangle 506 that can surround the hard core group can be determined, and the number of rows and columns of the constraint template can be determined according to the size of the minimum rectangle 506 and the size of the cell 508. For example, the number of rows and columns can be obtained by dividing the size of the minimum rectangle 506 by the size of the cell 508. Figure 5B An example is 3×3).

[0081] In step 3066, the constraint template is generated according to the number of rows and columns and the cell size.

[0082] Specifically, according to the determined cell size and number of rows and columns, a complete constraint template 510 can be generated, such as Figure 5C As shown. In addition, the origin of the constraint template can be further overlapped with the origin of the hard core group to prepare for subsequent template matching. The origin here can be divided into different types such as center, lower left, upper left, lower right, upper right, etc. for selection.

[0083] In step 3068, the hard core group is matched into cells of the constraint template.

[0084] The method of matching the constraint template may be different depending on whether the sizes of the hard cores in the hard core group are the same.

[0085] In some embodiments, when the sizes of the hard cores in the hard core group are the same, step 3068 may use the LP method to match the hard cores in the hard core group to the cells in the constraint template that are closest to them.

[0086] In some embodiments, when the sizes of the hard cores in the hard core group are different, Figure 3C As shown, step 3068 may further include:

[0087] In step 30682, in response to determining that there are at least two hard cores of different sizes in the hard core group, the hard cores in the hard core group whose sizes are larger than the cell size are divided into at least two sub-hard cores according to the cell size. In step 3062, the cell size is obtained by using the approximate greatest common divisor method. Therefore, for hard cores whose sizes are larger than the cell size, they can be basically (approximately equal to) integer multiples of the cell size. Based on this, the hard cores whose sizes are larger than the cell size can be divided according to the cell size to obtain an integer number of sub-hard cores. Fig. 6AAs shown, for a hard core whose size is approximately twice the size of a cell, it can be divided into two sub-hard cores. It can be understood that the method can be divided along the first direction and the second direction, which will not be described in detail here.

[0088] In step 30684, based on the mixed integer linear programming method, each hard core or sub-hard core in the hard core group is matched to the cell in the constraint template that is closest to it, and the sub-hard cores of the same hard core are placed in adjacent cells, such as Figure 6B shown.

[0089] In step 3070, in response to determining that there are closed areas or irregular areas between the matched hard core groups, the matched hard core groups are optimized for layout to eliminate the closed areas or the irregular areas.

[0090] A closed area (dead area) generally refers to an area surrounded by hard cores but in which standard units can be placed. This area may have a narrow channel connected to the outside world. By eliminating the closed area, the hard cores can be arranged more regularly and neatly, which is beneficial to timing optimization and winding. As an optional embodiment, it is possible to determine whether there are closed areas or irregular areas by determining the relationship between the number of hard cores in the hard core group and the number of cells in the constraint template. For example, when the number of hard cores in the hard core group is greater than the number of cells in the constraint template, it means that some cells are not filled with hard cores, which easily forms closed or irregular areas, thereby determining that there are closed areas or irregular areas between the hard core groups that have been matched.

[0091] In some embodiments, optimizing the layout of the matched hard core group to eliminate the closed area or the irregular area includes:

[0092] Taking the cells as units, scanning and calculating the contour cells and closed area cells or irregular area cells of the hard core;

[0093] Then, the contour line cells closest to the closed area cells may be filled with the closed area cells.

[0094] Specifically, the closed area cells can be filled with blank cells of the constraint template to update the constraint template, and the updated constraint template is a subset of the original template, and the number of cells is consistent with the number of hard cores. Then, step 3068 can be repeated based on the updated constraint template to eliminate the closed area or the irregular area.

[0095] Since the number of cells is consistent with the number of hard cores at this time, no closed or irregular regions will be formed after re-template matching, e.g. Figure 5D shown.

[0096] In some embodiments, if the hard core spacing in a unit cell is greater than the minimum constraint spacing, the unit cell size may be further reduced until the minimum constraint spacing to reduce the total area.

[0097] Therefore, in some embodiments, step 3072 may further include: adjusting the spacing of the hard core group after the optimized layout to compress the total area of ​​the constraint template; and outputting layout planning data based on the adjusted hard core group.

[0098] Specifically, in some embodiments, the spacing of the hard core groups after the optimized layout is adjusted to compress the total area of ​​the constraint template, such as Figure 6C shown.

[0099] At this point, the hard core group obtained is a hard core group that has been regularly aligned, which can better solve the problems that arise after mixed placement.

[0100] However, combined with the above, the automatic hard-core packing technology changes the result of mixed-place, which may affect the global optimization result of mixed-place. Therefore, the present application provides an interactive interface for users to use interactive operations to fine-tune the hard-core group that has been automatically packed, which can facilitate user use and improve development efficiency.

[0101] Fig. 7A The embodiment of the present application shows Figure 4 Schematic diagram of exemplary interface 700 after automatic hard core regularization alignment of the hard core group in region 40622.

[0102] like Fig. 7A As shown, the interface 700 (main page) can display a window 7064 (first window), in which the hardcore group after automatic regular alignment can be displayed, wherein the hardcores in the hardcore group can be adaptively and proportionally adjusted in size according to the size of the window 7064, so that the hardcores can be clearly displayed in the window 7064, which is convenient for user operation. Optionally, when the hardcore group is displayed in the window 7064, the constraint template 70642 for matching the hardcore group can also be displayed in the window 7064. The interface 700 can also display a window 7062 (second window), in which the initial layout planning data can be displayed. Optionally, the window 7062 and the window 7064 can be arranged side by side in the interface 700 for user viewing.

[0103] In some embodiments, Fig. 7A As shown, the computer device 100 can also automatically align the hard core group corresponding to the hard core group after the automatic alignment in the initial layout planning data of the window 7062 and display it in the window 7062, for example, display it in the window corresponding to the hard core group after the automatic alignment. Figure 4 Area 40622 corresponds to area 70622.

[0104] The user can adjust the position of the hard core in the window 7064 through interactive operation. Therefore, in step 308, in response to the interactive operation on the target hard core in the automatically aligned hard core group in the window 7064, the computer device 100 can adjust the position of the target hard core according to the interactive operation.

[0105] For example, the user may use a drag operation to adjust the position of the hard core in the window 7064. In response to the drag operation on the target hard core, the computer device 100 may move the target hard core to a position corresponding to the release position according to the release position of the drag operation.

[0106] As an optional embodiment, in response to determining that the release position is in a blank cell of the constraint template, the computer device 100 may move the target hard core to the blank cell.

[0107] It can be understood that the number of blank cells of constraint template 70642 is limited. In particular, after the closed area is eliminated during regular alignment, there are generally no blank cells.

[0108] Therefore, if the release position of the drag operation is in a non-blank cell of the constraint template 70642, and if the hard core in the non-blank cell is equal in size to the target hard core, the hard core in the non-blank cell is swapped with the target hard core.

[0109] like Figure 7B As shown, if the user selects the target hard core 70644 and follows Figure 7B Drag the target hard core 70644 in the direction of the middle arrow, and the release position of the drag operation is assumed to be Figure 7B The position pointed by the arrow in the figure can be swapped with the hard core 70644 and the hard core in the non-blank cell at that position. Figure 7C shown.

[0110] like Figure 7B and Figure 7C As shown, during the aforementioned interactive operation, the target hard core 70644 in window 7064 and the hard core corresponding to the target hard core 70644 in window 7062 can be highlighted, so that the user can easily observe the target hard core 70644 and the hard core corresponding to it in window 7062, which is convenient for user operation. Moreover, after the interactive operation ends, the target hard core 70644 and the hard core corresponding to it in window 7062 can remain highlighted until the next interactive operation starts.

[0111] In some embodiments, in addition to moving a single target hard core, multiple hard cores may be moved simultaneously.

[0112] like Fig.7D As shown, the user can select multiple target hard cores 70644 arranged in parallel along a first direction (vertical direction in the figure), and can drag multiple target hard cores 70644 along a second direction (the direction of the arrow in the figure, which is also horizontal). Assuming that the release positions of multiple target hard cores 70644 are in the non-blank cells of the constraint template 70642, if the hard cores in the non-blank cells match the size and shape of the multiple target hard cores, the hard cores in the non-blank cells can be swapped with the multiple target hard cores. Fig.7D As shown, assuming that the release position is the position pointed by the arrow, the hard core 70646 at this position occupies 4 cells along the first direction, and the multiple target hard cores 70644 also occupy 4 cells along the first direction, then it can be considered that the size (number of cells occupied) and shape (same extension direction) of the hard core 70646 and the multiple target hard cores 70644 match each other, so the two can be exchanged, as shown in FIG. Fig. 7E shown.

[0113] It can be understood that when the hard core in the non-blank cell does not match the size or shape of the multiple target hard cores 70644 selected by the user, the position exchange of the hard core cannot be completed when the drag operation is completed and released, and the interface 700 can be restored to the state before the interactive operation, for example, Fig.7D Status shown.

[0114] Taking into account issues such as deviation in user operations, in some embodiments, in addition to moving the target hard core to a non-blank cell to achieve hard core position exchange, the hard core position exchange can also be achieved by moving the target hard core between two adjacent non-blank cells.

[0115] In some embodiments, in response to determining that the release position is between two adjacent non-blank cells of the constraint template, if the hard core in the non-blank cell is equal in size to the target hard core, the hard core in the non-blank cell close to the target hard core in the two adjacent non-blank cells is translated in the direction along the center line of the two adjacent non-blank cells by a number of cells that match the size of the target hard core, and the target hard core is moved into the number of cells.

[0116] For example, when the size of the dragged target hard core occupies two cells, and the hard core in the non-blank cell close to the target hard core in two adjacent non-blank cells also occupies two cells, it is necessary to move the hard core in the non-blank cell close to the target hard core by two cells in the opposite direction of the target hard core's movement direction. In this way, two blank cells will be vacated at the corresponding positions, so that the target hard core can be placed in these two blank cells.

[0117] In some embodiments, multiple target hard cores may be moved simultaneously, so the aforementioned processing steps may need to be more complicated.

[0118] like Figure 7F As shown, the user selects two target hard cores 70644 at the same time and drags the two target hard cores 70644 in the direction of the arrow. The release position is the position pointed by the arrow, which is between two adjacent non-blank cells.

[0119] At this time, it is necessary to determine the number of cells occupied by the two target hard cores 70644 being dragged and their extension direction (two cells and the first direction in this embodiment), and then determine a number of hard cores on the side of the release position close to the target hard core 70644 that match the size and shape of the two target hard cores 70644 (the number of cells occupied and the direction of extension are the same), and then move these hard cores in the opposite direction of the target hard core movement by a number of cells (the number is equal to the number of cells occupied by the two target hard cores 70644), thereby freeing up these cells, and then placing the two target hard cores 70644 in them accordingly, as shown in FIG. Figure 7G shown.

[0120] This way, hardcore position swapping can be achieved even if the user does not accurately correspond the release position to the cell.

[0121] In some embodiments, Fig. 7A As shown, an adjacent mode option 7042 may also be displayed in the menu bar 704 of the interface 700 .

[0122] exist Fig. 7A In the interface 700 shown, if the user checks the adjacency mode option 7042, the computer device 100 can determine the hard core side without pins between the adjacent hard cores in the hard core group after the automatic regular alignment; then, according to the hard core side without pins, the adjacent hard cores are adjoined, and the interface 700 changes to the following. Figure 7H Interface 700 is shown.

[0123] In some embodiments, after the adjacency mode is turned on, the hard core sides without pins between adjacent hard cores along the first direction (vertical direction in the figure) and the second direction (horizontal direction in the figure) may be adjoined by default. At this time, the hard cores in the hard core group may not be adjusted in position, but adjoined according to the placement of the hard cores after mixed placement. Specifically, Figure 7H As shown in the figure, the sides of the hard core with pins are depicted with black bars (the sides without black bars are the sides of the hard core without pins). It can be seen that after the adjacency mode is turned on, the adjacent hard core sides without pins are adjacent.

[0124] To further adjust the adjacency mode, in some embodiments, such as Figure 7H As shown, the menu bar 704 may also display a first horizontal adjacent button 7044, a second horizontal adjacent button 7046, a first vertical adjacent button 7048, and a second vertical adjacent button 7050. By clicking these buttons, the user can implement further adjacent processing by reversing the placement of the hard core.

[0125] For example, according to the pattern of the first horizontal adjacent button 7044, when the first horizontal adjacent button 7044 is triggered, the hard core side located at the outermost side of the hard core group in the horizontal direction will not be provided with a pin. Figure 7H The leftmost row of hard cores in the middle hard core group should have no pins on the outermost side. Therefore, according to this standard, the hard cores can be placed in reverse so that their pins face inwards. Fig.7I As shown. In view of this, because the pins of the hard cores in the leftmost column of the hard core group face inward, a channel can be added there to facilitate wiring. Therefore, in order to save wiring area and make the layout more compact, the pins of the hard cores in another column close to the leftmost column of the hard core group can face the leftmost column of the hard core. In this way, the hard cores in adjacent columns can be routed in the same channel, thereby saving wiring area. By analogy, the adjacency processing of the entire hard core group is completed, as shown in Fig.7I shown.

[0126] For another example, according to the pattern of the second horizontal adjacent button 7046, when the second horizontal adjacent button 7046 is triggered, the hard core side located at the outermost side of the hard core group in the horizontal direction will need to be set with a pin. Figure 7H The leftmost column of hard cores in the middle hard core group should have pins on the outermost side. Therefore, according to this standard, Figure 7H The placement of the hard cores in the rightmost column can be reversed so that their pins face outwards, such as Figure 7JAs shown. In view of this, since the pins of the two outermost columns of hard cores are facing outward, the side of the adjacent column of hard cores without pins can be horizontally adjacent to the two outermost columns of hard cores. If there are pins on the side of the hard cores facing the two outermost columns of hard cores, the placement of the hard cores can be reversed to achieve horizontal adjacency. Further, the wiring channel can be set with reference to the previous embodiment. By analogy, the adjacency processing of the entire hard core group is completed, such as Figure 7J shown.

[0127] Similarly, vertical adjacency can refer to the processing method of horizontal adjacency, which will not be described here.

[0128] In this way, through adjacency processing, the hard core group layout is made more compact, and the layout result can be further optimized.

[0129] It should be noted that the aforementioned embodiment of fine-tuning the position of the hard core by interactive operation is performed after mixed placement and automatic regular alignment. Therefore, in order to maximize the optimized layout results of mixed placement and automatic regular alignment, the aforementioned interactive operation only provides limited operation methods. However, these interactive operations are very effective in providing users with space to further fine-tune the position of the hard core, thereby achieving the effect of further optimizing the layout and improving development efficiency.

[0130] In step 310 , layout planning data may be output based on the hard core group after position adjustment.

[0131] like Fig. 7A As shown, there are other hard cores remaining in the initial layout planning data that can be further processed. Therefore, as an optional embodiment, after completing the processing of a group of hard cores, another group of hard cores can be selected from the initial layout planning data and processed according to the aforementioned steps.

[0132] In some embodiments, after the user completes fine-tuning of the hard-core group, the hard-core group can be moved as a whole to the specified position of the entire layout plan in window 7062. The overall position movement of the hard-core group can be boundary movement, anchor point movement, and position movement. Among them, based on the boundary movement, a vertex of a certain boundary of the hard-core group can be used as a reference point, and then the reference point is used to align the entire hard-core group. Based on the anchor point movement, a vertex of a hard core in the hard-core group can be used as a reference point, and then the reference point is used to align the entire hard-core group. Based on the position movement, the drag distance and the drag release position can be directly calculated to move the hard-core group as a whole. The moved hard-core group can be as follows Figure 7K This process makes it easier to select and move the remaining hard cores.

[0133] Then, each aligned hard core group is moved as a whole to complete the splicing with other groups or hard cores according to the specified spacing and orientation.

[0134] The above operations are repeated until all hard cores in the initial layout planning data are organized and aligned.

[0135] Finally, the layout planning results are output.

[0136] It can be seen from the above embodiments that the layout planning method for chip design provided in the embodiments of the present application can align the mixed hard cores in an orderly manner, making subsequent power and ground wiring easier, saving winding resources, and making it easier to perform timing optimization and winding.

[0137] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0138] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0139] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute method 300 described in any of the above embodiments.

[0140] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0141] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 300 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0142] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors so that the processors execute the described method 300. Corresponding to the execution subject corresponding to each step in each embodiment of the method 300, the processor that executes the corresponding step may belong to the corresponding execution subject.

[0143] The computer program product of the above embodiment is used to enable the processor to execute the method 300 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0144] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0145] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0146] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0147] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. An interactive layout planning method for chip design, comprising: Reading the initial layout planning data of the chip design and displaying it on the main page; Determining a hard core group to be processed in the initial layout planning data, wherein the hard core group includes a plurality of hard cores; According to the automatic regular alignment algorithm, the hard core group to be processed is automatically regular aligned in the constraint template to obtain the hard core group after automatic regular alignment and display the hard core group after automatic regular alignment in the first window of the main page; In response to an interactive operation on a target hard core in the automatically aligned hard core group in the first window, adjusting a position of the target hard core according to the interactive operation; Output layout planning data based on the hard core group after position adjustment; The step of automatically aligning the hard core group to be processed in the constraint template according to the automatic alignment algorithm includes: Determining a cell size according to the hard core size of the hard core group to be processed; Determine the number of rows and columns of the constraint template; Generate the constraint template according to the number of rows and columns and the cell size; Matching the hard core group to be processed into cells of the constraint template; In response to determining that a closed area or an irregular area exists between the matched hard core groups, the matched hard core groups are optimized for layout to eliminate the closed area or the irregular area.

2. The method of claim 1, wherein: In response to an interactive operation on a target hard core in the automatically aligned hard core group in the first window, adjusting a position of the target hard core according to the interactive operation includes: In response to a drag operation on the target hard core, the target hard core is moved to a position corresponding to the release position according to a release position of the drag operation.

3. The method of claim 2, wherein: According to the release position of the drag operation, moving the target hard core to a position corresponding to the release position includes: In response to determining that the release position is in a blank cell of the constraint template, moving the target hard core into the blank cell; In response to determining that the release position is in a non-blank cell of the constraint template, if the hard core in the non-blank cell is equal in size to the target hard core, swapping the hard core in the non-blank cell with the target hard core; or In response to determining that the release position is between two adjacent non-blank cells of the constraint template, if the hard core in the non-blank cell is equal in size to the target hard core, the hard core in the non-blank cell close to the target hard core in the two adjacent non-blank cells is translated in the direction along the center line of the two adjacent non-blank cells by a number of cells matching the size of the target hard core, and the target hard core is moved into the number of cells.

4. The method of claim 2, wherein: The number of the target hard cores is multiple, and the multiple target hard cores are arranged in parallel along the first direction; In response to a drag operation on the target hard core, according to a release position of the drag operation, moving the target hard core to a position corresponding to the release position includes: In response to determining that the release position is in a non-blank cell of the constraint template, if the hard core in the non-blank cell matches the size and shape of the multiple target hard cores, the hard core in the non-blank cell is swapped with the multiple target hard cores.

5. The method of claim 2, wherein: The method further includes: displaying an adjacency mode option in the main page; Automatically aligning the hard core group to be processed in the constraint template includes: In response to determining that the adjacency mode option is checked, determining that there is no hard core side edge of a pin between adjacent hard cores in the hard core group after the automatic regular alignment; The adjacent hard cores are subjected to abutment processing according to the side edges of the hard cores.

6. The method of claim 2, wherein: Reading the initial layout planning data of the chip design and displaying it in a main page, including: displaying the initial layout planning data in a second window of the main page; arranging the first window and the second window side by side in the main page; While displaying the automatically aligned hard core group in the first window of the main page, the method further includes: The hard core groups in the initial layout planning data of the second window corresponding to the hard core groups after the automatic alignment are automatically aligned and displayed in the second window.

7. The method of claim 6, wherein: In response to an interactive operation on a target hard core in the automatically aligned hard core group in the first window, adjusting a position of the target hard core according to the interactive operation includes: The target hard core is highlighted in the first window and the second window.

8. The method of claim 1, wherein: Optimizing the layout of the matched hard core group to eliminate the closed area or the irregular area includes: Taking the cells as units, scanning and calculating the contour cells and closed area cells or irregular area cells of the hard core; The cells of the closed area closest to the contour cell are filled with the contour cell.

9. The method of claim 1, wherein: After optimizing the layout of the matched hard core group to eliminate the closed area or the irregular area, the method further includes: The spacing of the hard core groups after the optimized layout is adjusted to compress the total area of ​​the constraint template.

10. A computer device comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method of any one of claims 1 to 9.

12. A computer program product, comprising computer program instructions, which, when executed on a computer, cause the computer to execute the method according to any one of claims 1 to 9.

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