Semiconductor packaging structure and preparation method thereof, and electronic device

Abstract

The present application provides a semiconductor packaging structure and a method for preparing the same, as well as an electronic device. The structure comprises a first passivation layer, a redistribution layer, and a second passivation layer, wherein the redistribution layer is disposed on the first passivation layer; the second passivation layer is disposed on the first passivation layer and covers a portion of the redistribution layer, and the intersection angles of the first passivation layer, the second passivation layer, and the redistribution layer are right angles or obtuse angles. The technical solution of the present application can reduce the risk of holes on the basis of satisfying the working performance of the protective passivation layer, and avoid subsequent stress concentration that causes cracking of the passivation layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] In the semiconductor packaging structure, a protective passivation layer is formed above the redistribution layer, but bubbles are prone to exist in the protective passivation layer, which increases the risk of holes in the protective passivation layer. The increased risk of holes in the protective passivation layer is prone to cause cracks in the passivation layer under the subsequent board-level stress. How to reduce the risk of holes while meeting the working performance of the protective passivation layer and avoid subsequent stress concentration that causes cracks in the passivation layer is a topic that the industry continues to explore. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor packaging structure and a preparation method thereof, and an electronic device, which can reduce the risk of voids and avoid subsequent stress concentration that causes cracking of the passivation layer while meeting the working performance of the protective passivation layer.

[0004] In a first aspect of the present application, a semiconductor packaging structure is provided, comprising:

[0005] a first passivation layer;

[0006] a redistribution layer, the redistribution layer being disposed on the first passivation layer; and

[0007] The second passivation layer is disposed on the first passivation layer and covers a portion of the redistribution layer. The interface angles among the first passivation layer, the second passivation layer and the redistribution layer are right angles or obtuse angles.

[0008] It can be understood that, compared with the acute angle of the interface between the first passivation layer, the second passivation layer and the redistribution layer in the prior art, in the embodiment of the present application, the interface between the first passivation layer, the second passivation layer and the redistribution layer is changed to a right angle or an obtuse angle, which can ensure that the bubbles in the second passivation layer will not be blocked by the surrounding side of the redistribution layer when evaporating upward, so that they can be smoothly discharged into the external environment of the semiconductor packaging structure. In other words, it can ensure that the gas and solvent in the second passivation layer evaporate smoothly, thereby reducing the risk of bubbles in the second passivation layer, improving the yield of the semiconductor packaging structure, reducing the baking time required to prepare the semiconductor packaging structure, and improving the production efficiency of the semiconductor packaging structure.

[0009] In a possible implementation manner, a junction angle between the first passivation layer, the second passivation layer and the redistribution layer is within an angle range of 90°-135°.

[0010] In a possible implementation, the redistribution layer includes a bottom surface, a top surface, and a peripheral side surface connected between the top surface and the bottom surface, the bottom surface is in contact with the first passivation layer, the top surface and the peripheral side surface are in contact with the second passivation layer, and the orthographic projection of the top surface on the first passivation layer falls within the orthographic projection range of the bottom surface on the first passivation layer.

[0011] That is, the surface area of ​​the top surface of the redistribution layer is less than or equal to the surface area of ​​the bottom surface of the redistribution layer. Under this setting, the redistribution layer can form a structural layout with equal width from top to bottom or narrow at the top and wide at the bottom. Therefore, in the subsequent process steps of forming the second passivation layer, the redistribution layer can not hinder the evaporation process of the bubbles in the second passivation layer due to the structural layout with equal width from top to bottom or narrow at the top and wide at the bottom, and can smoothly guide the gas in the second passivation layer to volatilize to the external environment of the semiconductor packaging structure, playing a good guiding role. Exemplarily, the cross-sectional shape of the redistribution layer can be rectangular or trapezoidal.

[0012] In a possible implementation manner, the angle between the top surface and the peripheral side surface is a right angle or an obtuse angle.

[0013] In a possible application scenario, the surface area of ​​the top surface of the redistribution layer is smaller than the surface area of ​​the bottom surface of the redistribution layer, and the angle between the top surface of the redistribution layer and the peripheral side surface of the redistribution layer is an obtuse angle. Under this setting, the peripheral side surface of the redistribution layer can be an inclined surface inclined relative to the top surface of the redistribution layer. The inclined surface has a good guiding effect on the volatilization of the gas in the second passivation layer, which is beneficial to reduce the risk of holes in the second passivation layer, avoid the problem of cracking of the second passivation layer due to the presence of holes in subsequent processes, and have good reliability. Exemplarily, the angle range of the angle between the top surface of the redistribution layer and the peripheral side surface of the redistribution layer can be within the angle range of 90°-135° (including the endpoint values ​​90° and 135°).

[0014] In another possible application scenario, the surface area of ​​the top surface of the redistribution layer is equal to the surface area of ​​the bottom surface of the redistribution layer, and the angle between the top surface of the redistribution layer and the peripheral side surface of the redistribution layer is a right angle. Under this setting, the peripheral side surface of the redistribution layer can be a vertical surface set perpendicular to the top surface of the redistribution layer. The vertical surface will not block the volatilization of gas in the second passivation layer, which is conducive to reducing the risk of holes in the second passivation layer, avoiding the problem of cracking of the second passivation layer due to the presence of holes in subsequent processes, and having good reliability.

[0015] In a possible implementation manner, the peripheral side surface is connected to the top surface to form an outer top corner of the redistribution layer, and the outer top corner is a rounded corner.

[0016] It can be understood that when the angle between the top surface of the redistribution layer and the peripheral side surface of the redistribution layer becomes larger (such as the angle between the two is an obtuse angle), setting the outer top angle of the redistribution layer as a rounded transition is beneficial to reducing the adverse effects of stress in the semiconductor packaging structure, avoiding stratification between the redistribution layer and the second passivation layer, allowing the gas in the second passivation layer to easily flow to the external environment of the semiconductor packaging structure, reducing the risk of holes in the second passivation layer, and avoiding cracking of the second passivation layer.

[0017] In a possible implementation manner, the redistribution layer includes a plurality of circuits, and a spacing between two adjacent circuits is greater than or equal to 4 um.

[0018] As a result, the redistribution layer can be applied to packaging levels with low precision requirements, which is beneficial to reducing the production cost of the semiconductor packaging structure and improving the production efficiency of the semiconductor packaging structure.

[0019] In a possible implementation manner, the redistribution layer includes a plurality of circuits, and a line width of the circuits is greater than or equal to 4 um.

[0020] As a result, the redistribution layer can be applied to packaging levels with low precision requirements, which is beneficial to reducing the production cost of the semiconductor packaging structure and improving the production efficiency of the semiconductor packaging structure.

[0021] In a second aspect, the present application further provides an electronic device, comprising an electronic device and the semiconductor packaging structure as described above, wherein the electronic device is electrically connected to the semiconductor packaging structure.

[0022] In a third aspect, the present application further provides a method for preparing a semiconductor packaging structure, comprising:

[0023] providing a first passivation layer;

[0024] forming a redistribution layer on the first passivation layer;

[0025] A second passivation layer is formed on the first passivation layer, wherein the second passivation layer covers a portion of the redistribution layer, and a junction angle among the first passivation layer, the second passivation layer and the redistribution layer is a right angle or an obtuse angle.

[0026] In a possible implementation manner, forming a redistribution layer on the first passivation layer includes:

[0027] forming a first seed layer on the first passivation layer;

[0028] forming an initial photoresist layer on the first seed layer, wherein the initial photoresist layer is made of negative photoresist;

[0029] Patterning the initial photoresist layer to form a photoresist layer, wherein the photoresist layer exposes a portion of the first seed layer;

[0030] Filling a second seed layer in the photoresist layer so that the second seed layer is connected to the first seed layer to form an initial redistribution layer;

[0031] removing the photoresist layer;

[0032] The initial redistribution layer is etched to form the redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0034] Figure 2 It is a structural schematic diagram of a semiconductor packaging structure in the prior art;

[0035] Figure 3 It is another structural schematic diagram of a semiconductor packaging structure in the prior art;

[0036] Figure 4 is a schematic diagram of a first structure of a semiconductor packaging structure provided by an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a second structure of a semiconductor packaging structure provided by an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of a third structure of a semiconductor packaging structure provided by an embodiment of the present application;

[0039] Figure 7 It is another structural schematic diagram of a semiconductor packaging structure in the prior art;

[0040] Figure 8 is a fourth structural schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0041] Fig. 9 is a fifth structural schematic diagram of the semiconductor packaging structure provided by the embodiment of the present application;

[0042] Fig.10 It is a stress distribution diagram of an interface angle of the first passivation layer, the second passivation layer and the redistribution layer;

[0043] Fig.11 is a stress distribution diagram of another interface angle of the first passivation layer, the second passivation layer and the redistribution layer;

[0044] Fig.12 It is a schematic diagram of a structure in which the intersection angle of the first passivation layer, the second passivation layer and the redistribution layer is a right angle;

[0045] Fig.13 It is a schematic diagram of a structure in which the interface angle between the first passivation layer, the second passivation layer and the redistribution layer is an obtuse angle;

[0046] Fig.14 It is a structural schematic diagram in which the interface angle between the first passivation layer, the second passivation layer and the redistribution layer is an acute angle;

[0047] Fig.15 yes Fig.12 The stress distribution diagram when the interface angle is right angle is shown;

[0048] Fig.16 yes Fig.13 The stress distribution diagram when the interface angle is an obtuse angle is shown;

[0049] Fig.17 yes Fig.14 The stress distribution diagram shown is when the interface angle is acute;

[0050] Fig.18 is a schematic flow chart of a method for preparing a semiconductor packaging structure provided in an embodiment of the present application;

[0051] Fig.19 yes Fig.18 A schematic flow chart of the steps of a method for preparing a semiconductor packaging structure;

[0052] Fig. 20 yes Fig.18 A schematic diagram of the steps of the method for preparing the semiconductor packaging structure shown;

[0053] Fig.21 yes Fig.18 Another schematic diagram of the steps of the method for preparing the semiconductor packaging structure shown;

[0054] Fig. 22 yes Fig.18 A schematic diagram of the steps of the method for preparing the semiconductor packaging structure shown;

[0055] Fig.23 yes Fig.18 Another schematic diagram of the steps of the method for preparing a semiconductor packaging structure is shown. DETAILED DESCRIPTION

[0056] For ease of understanding, the terms involved in the embodiments of the present application are first explained.

[0057] And / or: It is just a way to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0058] Multiple: refers to two or more than two.

[0059] Connection: should be understood in a broad sense. For example, A and B are connected, which can be either direct or indirect through an intermediary.

[0060] The specific implementation of the present application will be clearly described below in conjunction with the accompanying drawings.

[0061] Embodiments of the present application provide a semiconductor packaging structure and a method for manufacturing the same, and an electronic device.

[0062] Among them, the electronic device can be but is not limited to smart consumer electronic devices such as mobile phones, tablets, laptops, switches, routers, or wearable electronic devices such as augmented reality (AR), virtual reality (VR), smart watches, smart bracelets, or vehicle-mounted devices such as car computers.

[0063] The following description will be made by taking a mobile phone as an example of the electronic device, but it should be understood that the invention is not limited thereto.

[0064] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 may include an electronic device 210 and a semiconductor package structure 100, and the electronic device 210 is electrically connected to the semiconductor package structure 100. It should be noted that the embodiment of the present application does not strictly limit the type of the electronic device 210, and the electronic device 210 that can be electrically connected to the semiconductor package structure 100 is within the scope of protection claimed in the embodiment of the present application.

[0065] Please refer to Figure 2 and Figure 3 , Figure 2 is a schematic diagram of a semiconductor packaging structure 1 in the prior art, Figure 3 1 is another structural schematic diagram of a semiconductor package structure 1 in the prior art. In the prior art, the semiconductor package structure 1 may include a Nitride (nitride) layer 2, an RDL (ReDistribution Layer, redistribution layer 30) layer 3 and a PI (Polyimide, polyimide) layer 4 stacked in sequence. Figure 2 As shown, bubbles generated by residual developer in the PI layer 4 are not completely removed, which makes it easy for holes 5 to exist in the PI layer 4. The existence of the holes 5 can easily cause the PI layer 4 to crack under the action of subsequent board-level stress, affecting the working reliability of the semiconductor packaging structure 1.

[0066] Therefore, the embodiment of the present application can provide a semiconductor packaging structure 100, which can reduce the risk of voids and avoid subsequent stress concentration leading to cracking of the passivation layer on the basis of satisfying the working performance of the passivation layer, which will be explained in detail below.

[0067] See also Figure 4 , Figure 4 1 is a schematic diagram of a first structure of a semiconductor package structure 100 provided in an embodiment of the present application. The semiconductor package structure 100 may include a substrate 10, a first passivation layer 20, a redistribution layer 30 and a second passivation layer 40.

[0068] The substrate 10 may be a silicon wafer to facilitate wafer-level packaging process. For example, the substrate 10 may be a silicon substrate or other semiconductor substrates.

[0069] The first passivation layer 20 is disposed on one side of the substrate 10. The first passivation layer 20 may be made of an inorganic material, such as a combination of one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or other suitable insulating materials. It is understood that the first passivation layer 20 may be used as an inter-layer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, or a combination of one or more of a passivation layer.

[0070] The redistribution layer 30 is disposed on the side of the first passivation layer 20 away from the substrate 10. Specifically, the redistribution layer 30 may include a top surface 31, a bottom surface 32, and a peripheral side surface 33. The bottom surface 32 of the redistribution layer 30 is a surface of the redistribution layer 30 that contacts the first passivation layer 20, the top surface 31 of the redistribution layer 30 is a surface of the redistribution layer 30 that faces away from the first passivation layer 20, and the peripheral side surface 33 of the redistribution layer 30 is a surface of the redistribution layer 30 that connects the top surface 31 of the redistribution layer 30 and the bottom surface 32 of the redistribution layer 30.

[0071] Please refer to Figure 4 and Figure 5 , Figure 5: is a second structural schematic diagram of the semiconductor packaging structure 100 provided in an embodiment of the present application. The orthographic projection of the top surface 31 of the redistribution layer 30 on the first passivation layer 20 can fall within the orthographic projection range of the bottom surface 32 of the redistribution layer 30. That is, the surface area of ​​the top surface 31 of the redistribution layer 30 is less than or equal to the surface area of ​​the bottom surface 32 of the redistribution layer 30. Under this setting, the redistribution layer 30 can form a structural layout with equal width from top to bottom or narrow at the top and wide at the bottom. Therefore, in the subsequent process steps of forming the second passivation layer 40, the redistribution layer 30 can not hinder the evaporation process of the bubbles in the second passivation layer 40 due to the structural layout with equal width from top to bottom or narrow at the top and wide at the bottom, and can smoothly guide the gas in the second passivation layer 40 to volatilize into the external environment of the semiconductor packaging structure 100, playing a good guiding role. Exemplarily, the cross-sectional shape of the redistribution layer 30 can be rectangular or trapezoidal.

[0072] In a possible implementation, Figure 4 As shown, the surface area of ​​the top surface 31 of the redistribution layer 30 is smaller than the surface area of ​​the bottom surface 32 of the redistribution layer 30, and the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 is an obtuse angle. Under this setting, the peripheral side surface 33 of the redistribution layer 30 can be an inclined surface inclined relative to the top surface 31 of the redistribution layer 30. The inclined surface has a good guiding effect on the volatilization of the gas in the second passivation layer 40, which is conducive to reducing the risk of holes in the second passivation layer 40, avoiding the problem of cracking of the second passivation layer 40 due to the presence of holes in the subsequent process, and having good reliability. Exemplarily, the angle range of the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 can be within the angle range of 90°-135° (including the endpoint values ​​90° and 135°).

[0073] In another possible implementation, Figure 5 As shown, the surface area of ​​the top surface 31 of the redistribution layer 30 is equal to the surface area of ​​the bottom surface 32 of the redistribution layer 30, and the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 is a right angle. Under this setting, the peripheral side surface 33 of the redistribution layer 30 can be a vertical surface set perpendicularly relative to the top surface 31 of the redistribution layer 30, and the vertical surface will not block the volatilization of the gas in the second passivation layer 40, which is conducive to reducing the risk of holes in the second passivation layer 40, avoiding the problem of cracking of the second passivation layer 40 due to the presence of holes in subsequent processes, and having good reliability.

[0074] In the embodiment of the present application, the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 may be connected to form an outer vertex 34 of the redistribution layer 30 , and the outer vertex 34 of the redistribution layer 30 may be covered by the second passivation layer 40 .

[0075] For a possible implementation, see Figure 4 The outer corner 34 of the redistribution layer 30 can be a sharp corner.

[0076] For another possible implementation, see Figure 6 , Figure 6 It is a third structural schematic diagram of the semiconductor packaging structure 100 provided in an embodiment of the present application. The outer top corner 34 of the redistribution layer 30 can be a rounded corner. It can be understood that when the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 becomes larger (such as the angle between the two is an obtuse angle), the outer top corner 34 of the redistribution layer 30 is set to a rounded transition, which is beneficial to reduce the adverse effects of stress in the semiconductor packaging structure 100, avoid delamination between the redistribution layer 30 and the second passivation layer 40, and make the gas in the second passivation layer 40 easily flow to the external environment of the semiconductor packaging structure 100, reduce the risk of holes in the second passivation layer 40, and avoid cracking of the second passivation layer 40.

[0077] Exemplarily, when the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 is 135°, the outer top corner 34 of the redistribution layer 30 is rounded, and the stress equivalent value at the outer top corner 34 of the redistribution layer 30 can be 1B. When the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 is 107.5°, the outer top corner 34 of the redistribution layer 30 is rounded, and the stress equivalent value at the outer top corner 34 of the redistribution layer 30 can be 1.29B. It can be seen that when the angle α1 between the top surface 31 of the redistribution layer 30 and the peripheral side surface 33 of the redistribution layer 30 becomes larger, rounding the outer top corner 34 of the redistribution layer 30 can have a better effect on the stress in the semiconductor packaging structure 100.

[0078] It should be noted that the fillet radius of the outer top corner 34 of the redistribution layer 30 can be selected according to the actual application scenario of the redistribution layer 30, and the embodiments of the present application do not impose strict limitations on this.

[0079] In the embodiment of the present application, the redistribution layer 30 may include a plurality of circuits (not shown), the line width of the circuit may be greater than or equal to 4um, and the spacing between two adjacent circuits may be greater than or equal to 4um. Thus, the redistribution layer 30 may be suitable for packaging levels with low precision requirements, which is beneficial to reducing the production cost of the semiconductor packaging structure 100 and improving the production efficiency of the semiconductor packaging structure 100.

[0080] Please refer again Figure 4, the second passivation layer 40 is disposed on the first passivation layer 20 and covers a portion of the redistribution layer 30. Specifically, the second passivation layer 40 covers the peripheral side surface 33 of the redistribution layer 30 and a portion of the top surface 31 of the redistribution layer 30, and another portion of the top surface 31 of the redistribution layer 30 is exposed through the opening 41 in the second passivation layer 40. Exemplarily, the material of the second passivation layer 40 may include polyimide (PI) or polybenzoxazole (PBO).

[0081] See also Figure 7 , Figure 7 It is another structural schematic diagram of a semiconductor packaging structure 100 in the prior art. Figure 7 The arrow in the middle shows the evaporation path of the gas. It can be seen that the interface angle β1 of the Nitride layer 2, the RDL layer 3 and the PI layer 4 is an acute angle. Under this setting, during the baking and evaporation removal stage of the developer, the bevel will easily gather bubbles, and this bevel will have a certain blocking effect on the upward evaporation of the gas in the PI layer 4, causing the PI layer 4 to be susceptible to stress and crack at the interface of the Nitride layer 2, the RDL layer 3 and the PI layer 4.

[0082] Please refer to Figure 8 and Fig. 9 , Figure 8 is a fourth structural schematic diagram of the semiconductor package structure 100 provided in an embodiment of the present application, Fig. 9 1 is a fifth structural diagram of the semiconductor package structure 100 provided in the embodiment of the present application. Figure 8 and Fig. 9 The arrow in the middle shows the evaporation path of the gas. The interface angle α2 between the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 can be a right angle or an obtuse angle.

[0083] Exemplarily, the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is in the range of 90°-135° (including the end values ​​90° and 135°). Fig.10 and Fig.11 , Fig.10 is a stress distribution diagram of a junction angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30, Fig.11 α2 is another stress distribution diagram of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 at an interface angle α2. Fig.10 The interface angle α2 among the first passivation layer 20 , the second passivation layer 40 and the redistribution layer 30 is 107.5°, and the stress equivalent value may be 1.07A. Fig.11The interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is 135°, and the stress equivalent value can be 1A. It can be seen that the larger the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30, the gentler the slope of the redistribution layer 30, the smaller the influence on the stress, and the easier it is for the gas in the second passivation layer 40 to flow away.

[0084] It can be understood that, compared with the prior art in which the interface angles of the first passivation layer, the second passivation layer and the redistribution layer are acute angles, in the embodiment of the present application, the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is changed to a right angle or an obtuse angle, which can ensure that the bubbles in the second passivation layer 40 will not be blocked by the peripheral side surface 33 of the redistribution layer 30 when evaporating upward, so that they can be smoothly discharged into the external environment of the semiconductor packaging structure 100. In other words, it can ensure that the gas and solvent in the second passivation layer 40 evaporate smoothly, thereby reducing the risk of bubbles in the second passivation layer 40, improving the yield of the semiconductor packaging structure 100, reducing the baking time required for preparing the semiconductor packaging structure 100, and improving the production efficiency of the semiconductor packaging structure 100.

[0085] For example, please refer to Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 , Fig.12 2 is a schematic diagram of a structure in which the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is a right angle. Fig.13 2 is a schematic diagram of a structure in which the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an obtuse angle. Fig.14 2 is a schematic diagram of a structure in which the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an acute angle. Fig.15 yes Fig.12 The stress distribution diagram when the intersection angle α2 is a right angle is shown. Fig.16 yes Fig.13 The stress distribution diagram when the intersection angle α2 is an obtuse angle is shown. Fig.17 yes Fig.14 The stress distribution diagram shows that the intersection angle α2 is an acute angle.

[0086] The semiconductor package structure 100 may further include a conductive structure 50, which is disposed on the redistribution layer 30 and covers a portion of the second passivation layer 40, and the conductive structure 50 is electrically connected to the redistribution layer 30. The conductive structure 50 may include an under-bump metallurgy (UBM) layer 51 and solder balls 52 on the under-bump metallurgy layer.

[0087] Combined with reference Figure 12-Figure 17 , it can be seen that Fig.12 The interface angle α2 among the first passivation layer 20 , the second passivation layer 40 and the redistribution layer 30 is a right angle, and the stress equivalent value may be 1.06C. Fig.13 The interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an obtuse angle, and the stress equivalent value can be 1C. Fig.14 The interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an acute angle, and the stress equivalent value can be 1.07 C. Therefore, compared with the solution in which the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an acute angle or a right angle, the solution in which the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is an obtuse angle can reduce the risk of overall mechanical stress of the semiconductor package structure 100 and has good reliability.

[0088] The embodiment of the present application also provides a method for preparing a semiconductor package structure 100. For the structure of the semiconductor package structure 100, please refer to Figure 1-Figure 17 And the above description is not repeated here. Figure 1-Figure 17 The semiconductor package structure 100 shown in FIG. 1 is taken as an example for further description. The following description of the semiconductor package structure 100 can be applied to the aforementioned Figure 1-Figure 17 In the semiconductor package structure 100.

[0089] Please refer to Figure 4 and Fig.18 , Fig.18 1 is a flow chart of a method for manufacturing a semiconductor package structure 100 provided in an embodiment of the present application. The method for manufacturing the semiconductor package structure 100 may at least include S100, S200 and S300, which are described in detail as follows.

[0090] S100 : providing a first passivation layer 20 .

[0091] S200 : forming a redistribution layer 30 on the first passivation layer 20 .

[0092] S300: forming a second passivation layer 40 on the first passivation layer 20, wherein the second passivation layer 40 covers a portion of the redistribution layer 30, and an interface angle α2 among the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is a right angle or an obtuse angle.

[0093] Each step will be further described below.

[0094] The following will be combined Figure 4 and Fig.18 The above step S100 will be described.

[0095] S100 : providing a first passivation layer 20 .

[0096] The first passivation layer 20 may cover the substrate 10 .

[0097] The following will be combined Fig.19 , Fig. 20 and Fig.21 To describe the above step S200, Fig.19 yes Fig.18 FIG. 1 is a flow chart of step S200 of the method for preparing the semiconductor package structure 100. Fig. 20 yes Fig.18 A schematic diagram of step S200 of the method for preparing the semiconductor package structure 100 is shown. Fig.21 yes Fig.18 Another schematic diagram of step S200 of the method for preparing the semiconductor package structure 100 is shown. Fig. 20 and Fig.21 The first passivation layer 20 is not shown in the figures, but it should be understood that this is not limiting.

[0098] S200 : forming a redistribution layer 30 on the first passivation layer 20 .

[0099] Step S200 may include at least steps S210, S220, S230, S240, S250 and S260, which are described in detail as follows:

[0100] S210 : forming a first seed layer 35 on the first passivation layer 20 .

[0101] The first seed layer 35 may be made of copper.

[0102] S220 : forming an initial photoresist layer 60 on the first seed layer 35 , wherein the initial photoresist layer 60 is made of negative photoresist.

[0103] S230 : patterning the initial photoresist layer 60 to form a photoresist layer 61 , wherein the photoresist layer 61 exposes a portion of the first seed layer 35 .

[0104] The patterning may include using a mask plate 70 to perform exposure and development on the initial photoresist layer 60 .

[0105] S240 : filling the second seed layer 36 in the photoresist layer 61 , so that the second seed layer 36 is connected to the first seed layer 35 to form an initial redistribution layer 37 .

[0106] The second seed layer 36 may be made of copper.

[0107] S250 : removing the photoresist layer 61 .

[0108] S260 : etching the initial redistribution layer 37 to form a redistribution layer 30 .

[0109] The following will be combined Fig. 22 and Fig.23 To describe the above step S300, Fig. 22 yes Fig.18 A schematic diagram of step S300 of the method for preparing the semiconductor package structure 100 is shown. Fig.23 yes Fig.18 Another schematic diagram of step S300 of the method for preparing the semiconductor package structure 100 is shown. Fig. 22 and Fig.23 Not drawn in.

[0110] S300: forming a second passivation layer 40 on the first passivation layer 20, wherein the second passivation layer 40 covers a portion of the redistribution layer 30, and an interface angle α2 among the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 is a right angle or an obtuse angle.

[0111] Under this setting, the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 can be Fig. 22 Alternatively, the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 may be Fig.23 Obtuse angle shown.

[0112] It is understandable that this solution can directly change the interface angle α2 of the first passivation layer 20, the second passivation layer 40 and the redistribution layer 30 to a right angle or an obtuse angle through the solution of negative photoresist, thereby avoiding stress concentration caused by sharp edge angles, thereby improving the evaporation path of the developer without hindering the volatilization of bubbles and reducing the stress of the semiconductor packaging structure 100. And for positive and negative photoresists of the same thickness, during the wet etching process, the negative photoresist will perform better in speed and graphics. As a result, the curing time of the second passivation layer 40 can be shortened, the filling effect of the second passivation layer 40 can be improved, the risk of holes in the second passivation layer 40 can be reduced, and the subsequent stress concentration caused to cause the second passivation layer 40 to crack can be avoided.

[0113] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: a first passivation layer; A redistribution layer, the redistribution layer being disposed on the first passivation layer; and A second passivation layer, the second passivation layer is arranged on the first passivation layer and covers a portion of the redistribution layer, the second passivation layer is formed by heat treatment of baking with a developer and curing, the material of the second passivation layer includes polyimide or polybenzoxazole, the intersection angle between the first passivation layer, the second passivation layer and the redistribution layer is a right angle or an obtuse angle, and the intersection angle between the first passivation layer, the second passivation layer and the redistribution layer is positively correlated with the gas discharge rate in the second passivation layer.

2. The semiconductor package structure according to claim 1, wherein: The interface angles of the first passivation layer, the second passivation layer and the redistribution layer are within the range of 90°-135°.

3. The semiconductor package structure according to claim 1 or 2, characterized in that: The redistribution layer includes a bottom surface, a top surface, and a peripheral side surface connected between the top surface and the bottom surface, the bottom surface is in contact with the first passivation layer, the top surface and the peripheral side surface are in contact with the second passivation layer, and the orthographic projection of the top surface on the first passivation layer falls within the orthographic projection range of the bottom surface on the first passivation layer.

4. The semiconductor package structure according to claim 3, wherein: The angle between the top surface and the peripheral side surface is a right angle or an obtuse angle.

5. The semiconductor package structure according to claim 3, wherein: The peripheral side surface is connected to the top surface to form an outer top corner of the redistribution layer, and the outer top corner is a rounded corner.

6. The semiconductor package structure according to any one of claims 1, 2, 4-5, characterized in that: The redistribution layer includes a plurality of circuits, and a spacing between two adjacent circuits is greater than or equal to 4 um.

7. The semiconductor package structure according to any one of claims 1, 2, 4-5, characterized in that: The redistribution layer includes a plurality of circuits, and the line width of the circuits is greater than or equal to 4 um.

8. An electronic device, characterized in that: The electronic device comprises an electronic device and a semiconductor package structure as claimed in any one of claims 1 to 7, wherein the electronic device is electrically connected to the semiconductor package structure.

9. A method for preparing a semiconductor packaging structure, characterized in that: include: providing a first passivation layer; forming a redistribution layer on the first passivation layer; A second passivation layer is formed on the first passivation layer, the second passivation layer covers a portion of the redistribution layer, the second passivation layer is formed by heat treatment of baking with a developer and curing, the material of the second passivation layer includes polyimide or polybenzoxazole, the intersection angle between the first passivation layer, the second passivation layer and the redistribution layer is a right angle or an obtuse angle, and the intersection angle between the first passivation layer, the second passivation layer and the redistribution layer is positively correlated with the gas discharge rate in the second passivation layer.

10. The method according to claim 9, characterized in that The forming of a redistribution layer on the first passivation layer comprises: forming a first seed layer on the first passivation layer; forming an initial photoresist layer on the first seed layer, wherein the initial photoresist layer is made of negative photoresist; Patterning the initial photoresist layer to form a photoresist layer, wherein the photoresist layer exposes a portion of the first seed layer; Filling a second seed layer in the photoresist layer so that the second seed layer is connected to the first seed layer to form an initial redistribution layer; removing the photoresist layer; The initial redistribution layer is etched to form the redistribution layer.

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