High-precision switched capacitor integrating circuit based on negative capacitance auxiliary CLS technology

Abstract

The invention discloses a high-precision switched capacitor integrating circuit based on a negative capacitance auxiliary type CLS technology, and the circuit comprises a clock control circuit, a switched capacitor network, an adjustable capacitor array, a differential operational amplifier and a CLS network, one end is connected with the inverting input end of the differential operational amplifier, and the other end is connected with the inverting output end of the differential operational amplifier. And one end of the second adjustable capacitor sub-array of the adjustable capacitor array is connected with the normal phase input end of the operational amplifier, and the other end of the second adjustable capacitor sub-array is connected with the normal phase output end of the operational amplifier. Through the connection mode, the Miller effect can be utilized, and the adjustable capacitor array is equivalent to a negative capacitor at the input end of the differential operational amplifier, so that charge sharing between a capacitor in a switched capacitor network and a capacitor in a CLS network is avoided, and the precision of the circuit is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS (Correlated-Level_Shifting, correlated level shifting) technology. Background Art

[0002] Switched capacitor integrator circuits are widely used in high-precision, small-bandwidth sigma delta ADCs (analog-to-digital converters) because of their simple structure. High-precision sigma delta ADCs place higher demands on the gain of the operational amplifier in the switched capacitor integrator circuit. Switched capacitor integrator circuits implemented by operational amplifiers with insufficient gain will produce integration errors, which are directly related to the performance of the circuit.

[0003] In order to solve this problem, a CLS network is usually added to the output port of the operational amplifier in the existing switched capacitor integration circuit, and reasonable clock control is adopted to alleviate the integration error phenomenon. However, the charge sharing between the capacitor in the added CLS network and the sampling integration capacitor in the switched capacitor integration circuit will limit the improvement of the accuracy of the switched capacitor integration circuit.

[0004] Therefore, how to provide a high-precision switched capacitor integration circuit has become a problem that needs to be solved urgently. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology, wherein the high-precision switched capacitor integration circuit comprises a clock control circuit, a switched capacitor network, an adjustable capacitor array, a differential operational amplifier, and a CLS network;

[0008] The clock control circuit is used to generate a two-phase non-overlapping clock and a CLS clock; the CLS clock is used to control the switching of switches in the CLS network;

[0009] The switch capacitor network is used to sample the positive and negative electrodes of the input terminal under the control of the two-phase non-overlapping clock to obtain a positive sampling signal and a negative sampling signal; integrate the positive sampling signal and the negative sampling signal to output a positive integrated signal and a negative integrated signal;

[0010] The differential operational amplifier is used to transfer the charge on the sampling capacitor in the switched capacitor network to the integrating capacitor when integrating the positive sampling signal and the negative sampling signal in the switched capacitor network, and output a first differential amplified signal and a second differential amplified signal;

[0011] The CLS network has one end connected to the first differential amplified signal and the second differential amplified signal, and the other end connected to the positive integral signal and the negative integral signal, and the CLS network is used to perform relevant level shift on the first differential amplified signal and the second differential amplified signal under the control of the CLS clock to alleviate the integral error of the positive integral signal and the negative integral signal;

[0012] The adjustable capacitor array comprises a first adjustable capacitor subarray and a second adjustable capacitor subarray; one end of the first adjustable capacitor subarray is connected to the inverting input end of the differential operational amplifier, and the other end is connected to the inverting output end of the differential operational amplifier; one end of the second adjustable capacitor subarray is connected to the non-inverting input end of the operational amplifier, and the other end is connected to the non-inverting output end of the operational amplifier.

[0013] Optionally, the clock control circuit includes a buffer, a frequency divider, a two-phase non-overlapping clock module and a combinational logic circuit;

[0014] The input end of the buffer is connected to the external clock, the first output end of the buffer is connected to the input end of the frequency divider, the second output end of the buffer is connected to the first input end of the combinational logic circuit, the output end of the frequency divider is connected to the input end of the two-phase non-overlapping clock module, the first output end of the two-phase non-overlapping module outputs the two-phase non-overlapping clock, and the second output end of the two-phase non-overlapping module is connected to the second input end of the combinational logic circuit; the combinational logic circuit is used to perform a logical combination operation on the clock received at its second input end and the clock received at its first input end to output the CLS clock; the CLS clock includes no clocks Φ that are simultaneously at a high level 11 and clock Φ 12 The two-phase non-overlapping clock module is used to perform two-phase non-overlapping clock processing on the input clock to obtain the two-phase non-overlapping clock; the two-phase non-overlapping clock includes a clock S1 and a clock S2 that do not have a high level at the same time and a delayed signal S of the clock S1. 1D and the delayed signal S of the clock S2 2D .

[0015] Optionally, the switched capacitor network includes a first switched capacitor network and a second switched capacitor network;

[0016] The first switch capacitor network includes: a sampling capacitor C1, an integrating capacitor C3, a gate voltage bootstrap switch K1, a CMOS switch K3, a CMOS switch K5 and a CMOS switch K7;

[0017] The first end of the gate voltage bootstrap switch K1 is connected to the positive electrode, the second end of the gate voltage bootstrap switch K1 is connected to the first end of the sampling capacitor C1, the first end of the CMOS switch K3 is connected to the common mode voltage, the second end of the CMOS switch K3 is connected to the first end of the sampling capacitor C1, the second end of the sampling capacitor C1 is connected to the first end of the CMOS switch K7, the first end of the CMOS switch K5 is connected to the common mode voltage, the second end of the CMOS switch K5 is connected to the second end of the sampling capacitor C1, the second end of the CMOS switch K7 outputs the positive sampling signal, the first end of the integration capacitor C3 is connected to the positive sampling signal, the second end of the integration capacitor C3 is connected to the first output end of the CLS network, and outputs a positive integration signal;

[0018] The second switch capacitor network includes a sampling capacitor C2, an integrating capacitor C4, a gate voltage bootstrap switch K2, a CMOS switch K4, a CMOS switch K6 and a CMOS switch K8;

[0019] The first end of the gate voltage bootstrap switch K2 is connected to the negative electrode, the second end of the gate voltage bootstrap switch K2 is connected to the first end of the sampling capacitor C2, the first end of the CMOS switch K4 is connected to the common mode voltage, the second end of the CMOS switch K4 is connected to the first end of the sampling capacitor C2, the second end of the sampling capacitor C2 is connected to the first end of the CMOS switch K8, the first end of the CMOS switch K6 is connected to the common mode voltage, the second end of the CMOS switch K6 is connected to the second end of the sampling capacitor C2, the second end of the CMOS switch K8 outputs the negative electrode sampling signal, the first end of the integration capacitor C4 is connected to the negative electrode sampling signal, the second end of the integration capacitor C4 is connected to the second output end of the CLS network, and outputs a negative electrode integration signal.

[0020] Optionally, the CLS network includes a first CLS sub-network and a second CLS sub-network;

[0021] The first CLS sub-network includes a switch K9, a switch K11, a switch K13 and a capacitor C7;

[0022] The first end of the switch K9 is connected to the common mode voltage, the second end of the switch K9 is connected to the first end of the capacitor C7, the first end of the switch K11 is connected to the first differential amplified signal, the second end of the switch K11 is connected to the first end of the capacitor C7, the first end of the switch K13 is connected to the first differential amplified signal, the second end of the switch K13 is connected to the second end of the capacitor C7, and the second end of the capacitor C7 is connected to the positive electrode integrated signal;

[0023] The second CLS sub-network includes a switch K10, a switch K12, a switch K14 and a capacitor C8;

[0024] The first end of the switch K10 is connected to the common mode voltage, the second end of the switch K10 is connected to the first end of the capacitor C8, the first end of the switch K12 is connected to the second differential amplified signal, the second end of the switch K12 is connected to the first end of the capacitor C8, the first end of the switch K14 is connected to the second differential amplified signal, the second end of the switch K14 is connected to the second end of the capacitor C8, and the second end of the capacitor C8 is connected to the negative electrode integrated signal.

[0025] Optionally, the capacitance of the first adjustable capacitor array is smaller than the capacitance of the integral capacitor in the first switched capacitor network; and the capacitance of the second adjustable capacitor array is smaller than the capacitance of the integral capacitor in the second switched capacitor network.

[0026] Optionally, both the first adjustable capacitor subarray and the second adjustable capacitor subarray are binary code capacitor arrays or thermometer code capacitor arrays.

[0027] Optionally, the differential operational amplifier is a fully differential inverter-type operational amplifier.

[0028] In a second aspect, the present invention provides a sigma delta analog-to-digital converter, comprising any one of the above-mentioned high-precision switched capacitor integration circuits.

[0029] The present invention provides a high-precision switched capacitor integrator circuit based on negative capacitance assisted CLS technology, wherein one end of the first adjustable capacitor subarray of the adjustable capacitor array is connected to the inverting input of the differential operational amplifier, and the other end is connected to the inverting output of the differential operational amplifier. The second adjustable capacitor subarray of the adjustable capacitor array, one end of which is connected to the non-inverting input of the operational amplifier, and the other end of which is connected to the non-inverting output of the operational amplifier. Through this connection mode, the Miller effect can be utilized to make the adjustable capacitor array equivalent to a negative capacitor at the input of the differential operational amplifier. When the absolute size of the equivalent negative capacitor is close to the capacitance of the capacitor in the switched capacitor network, it can be approximated to eliminate the capacitor in the switched capacitor network, thereby avoiding charge sharing between the capacitor in the switched capacitor network and the capacitor in the CLS network, and effectively improving the accuracy of the circuit.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology provided by an embodiment of the present invention;

[0032] Figure 2 is a schematic structural diagram of a clock control circuit provided by an embodiment of the present invention;

[0033] Figure 3 is a timing diagram of a two-phase non-overlapping clock and a CLS clock provided by an embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of the structure of an integrator provided by an embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of the structure of a gate voltage bootstrap switch provided by an embodiment of the present invention;

[0036] Figure 6 is a schematic diagram of the structure of a CMOS switch provided by an embodiment of the present invention;

[0037] Figure 7 is a schematic structural diagram of a binary code capacitor array provided by an embodiment of the present invention;

[0038] Figure 8 Schematic diagram of the structure of a fully differential inverter-type operational amplifier provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0040] In order to solve the problem that the charge sharing between the capacitor in the CLS network added in the existing switched capacitor integration circuit and the sampling integration capacitor in the switched capacitor integration circuit limits the accuracy improvement of the switched capacitor integration circuit, an embodiment of the present invention provides a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology, see Figure 1 , Figure 1 It is a structural schematic diagram of a high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology provided by an embodiment of the present invention. The high-precision switched capacitor integration circuit includes a clock control circuit, a switched capacitor network, an adjustable capacitor array, a differential operational amplifier and a CLS network.

[0041] The clock control circuit is used for generating a two-phase non-overlapping clock and a CLS clock; the CLS clock is used for controlling the switching of switches in the CLS network.

[0042] In the embodiment of the present invention, the clock control circuit receives an external clock, and then generates a two-phase non-overlapping clock and a CLS clock based on the external clock. The external clock may be generated by an external circuit or device.

[0043] The two-phase non-overlapping clock refers to two clocks that do not overlap each other, that is, when the clock S1 and the clock S2 in the two-phase non-overlapping clock are not at a high level at the same time.

[0044] In the embodiment of the present invention, the two-phase non-overlapping clock is used to control the switching of switches in the switched capacitor network, and the CLS clock is used to control the switching of switches in the CLS network.

[0045] The switched capacitor network is used to sample the positive and negative signals of the input terminal under the control of a two-phase non-overlapping clock to obtain a positive sampling signal and a negative sampling signal; integrate the positive sampling signal and the negative sampling signal to output a positive integrated signal and a negative integrated signal.

[0046] In an embodiment of the present invention, the switched capacitor network is a network composed of a sampling capacitor, an integrating capacitor and a switch controlled by a clock, wherein the switch in the switched capacitor network is controlled by a two-phase non-overlapping clock generated by a clock control circuit.

[0047] In the embodiment of the present invention, the switched capacitor network is divided into a sampling phase and an integration phase when working. In the sampling phase, the two-phase non-overlapping clock controls the on-off of the switch in the switched capacitor network, and uses the sampling capacitor to input the positive electrode IN P and negative IN NThe signal is sampled to obtain a positive sampling signal and a negative sampling signal. In the integration stage, the two-phase non-overlapping clock controls the on and off of the switch in the switch capacitor network to transfer the charge in the sampling capacitor to the integration capacitor, integrate the positive sampling signal and the negative sampling signal, and output the positive integration signal and the negative integration signal.

[0048] The differential operational amplifier is used to transfer the charge on the sampling capacitor in the switched capacitor network to the integrating capacitor when integrating the positive sampling signal and the negative sampling signal in the switched capacitor network, and output a first differential amplified signal and a second differential amplified signal.

[0049] In the embodiment of the present invention, the differential operational amplifier has two inputs and two outputs, wherein the two inputs refer to the positive sampling signal and the negative sampling signal sampled by the switch capacitor network in the sampling phase. The two outputs refer to the first differential amplified signal and the second differential amplified signal outputted by transferring the charge on the sampling capacitor in the switch capacitor network to the integrating capacitor when the differential operational amplifier integrates the positive sampling signal and the negative sampling signal in the switch capacitor network.

[0050] In an embodiment of the present invention, a CLS network has one end connected to a first differential amplified signal and a second differential amplified signal, and the other end connected to a positive integral signal and a negative integral signal. The CLS network is used to perform related level shifting on the first differential amplified signal and the second differential amplified signal under the control of a CLS clock to alleviate the integration error of the positive integral signal and the negative integral signal.

[0051] The on and off of the switches in the CLS network are controlled by the CLS clock generated by the clock control circuit. By controlling the switching of the switches in the CLS network, the CLS is reversed so that the difference between the first differential amplified signal and the second differential amplified signal output from the differential operational amplifier approaches 0. According to the input and output principle of the differential operational amplifier, the difference in the input of the differential operational amplifier also approaches 0, thereby alleviating the integration error of the positive integral signal and the negative integral signal.

[0052] However, charge sharing occurs between the capacitors in the CLS network and the capacitors in the switched capacitor network, limiting the integration accuracy. In order to solve this problem, the high-precision switched capacitor integration circuit provided in an embodiment of the present invention includes an adjustable capacitor array. Among them, the adjustable capacitor array includes a first adjustable capacitor subarray and a second adjustable capacitor subarray; the first adjustable capacitor subarray, one end of which is connected to the inverting input terminal of the differential operational amplifier, and the other end of which is connected to the inverting output terminal of the differential operational amplifier; the second adjustable capacitor subarray, one end of which is connected to the non-inverting input terminal of the operational amplifier, and the other end of which is connected to the non-inverting output terminal of the operational amplifier.

[0053] In the embodiment of the present invention, the connection mode of the adjustable capacitor array is a positive feedback connection, which is equivalent to making the capacitance of the adjustable capacitor equivalent to a negative value at the input port of the differential operational amplifier through the Miller effect. The absolute size of the negative capacitance is related to the gain of the differential operational amplifier and the capacitance of the connected adjustable capacitor array.

[0054] In an embodiment of the present invention, the first adjustable capacitor subarray of the adjustable capacitor array has one end connected to the inverting input terminal of the differential operational amplifier, and the other end connected to the inverting output terminal of the differential operational amplifier. The second adjustable capacitor subarray of the adjustable capacitor array has one end connected to the non-inverting input terminal of the operational amplifier, and the other end connected to the non-inverting output terminal of the operational amplifier. Through this connection method, the Miller effect can be utilized to make the adjustable capacitor array equivalent to a negative capacitor at the input terminal of the differential operational amplifier. When the absolute size of the equivalent negative capacitor is close to the capacitance of the capacitor in the switched capacitor network, it can be approximated to eliminate the capacitor in the switched capacitor network, thereby avoiding charge sharing between the capacitor in the switched capacitor network and the capacitor in the CLS network, and effectively improving the accuracy of the circuit.

[0055] See also Figure 2 , Figure 2 The clock control circuit provided by the embodiment of the present invention is a schematic diagram of the structure of the clock control circuit, which includes a buffer, a frequency divider, a two-phase non-overlapping clock module and a combinational logic circuit. The connection relationship is as follows: the input end of the buffer is connected to the external clock, the first output end of the buffer is connected to the input end of the frequency divider, the second output end of the buffer is connected to the first input end of the combinational logic circuit, the output end of the frequency divider is connected to the input end of the two-phase non-overlapping clock module, the first output end of the two-phase non-overlapping module outputs the two-phase non-overlapping clock, and the second output end of the two-phase non-overlapping module is connected to the second input end of the combinational logic circuit.

[0056] The combinational logic circuit is used to perform a logical combination operation on the clock received at its second input terminal and the clock received at its first input terminal to output a CLS clock; wherein the clock input to the first input terminal of the combinational logic circuit is the clock after passing through the buffer, and the clock input to the second input terminal of the combinational logic circuit is the clock output by the two-phase non-overlapping clock module. The CLS clock includes no clocks Φ that are simultaneously at a high level. 11 and clock Φ 12 The two-phase non-overlapping clock module is used to process the input clock into a two-phase non-overlapping clock to obtain a two-phase non-overlapping clock; the two-phase non-overlapping clock includes a clock S1 and a clock S2 that are not simultaneously high, and a delayed signal S of the clock signal S1. 1D and the delayed signal S of the clock signal S2 2D .

[0057] The following will be combined Figure 3, the clock control circuit in the embodiment of the present invention is described by taking an example, Figure 3 It is a timing diagram of a two-phase non-overlapping clock and a CLS clock provided by an embodiment of the present invention.

[0058] The buffer is used to connect the external clock and output a square wave signal 1 with smaller rising and falling edges. The square wave signal 1 is output through the frequency divider as a square wave signal 2 with half the frequency of the square wave signal 1. The square wave signal 2 is then transmitted to the two-phase non-overlapping module and the combinational logic circuit.

[0059] The two-phase overlapping clock module performs two-phase non-overlapping processing on the input square wave signal 2 to generate clocks S1, S2, and S 1D and clock S 2D , where clock S1 and clock S2 do not have high level clocks at the same time. 1D is the delayed signal of clock S1, clock S 2D is the delayed signal of clock S2. 1D The rising edge of clock S2 is almost the same as the rising edge of clock S1, and its falling edge is slightly later than the falling edge of clock S1, with a certain delay. 2D The use of delayed signals will help eliminate clock feedthrough.

[0060] The following example is used to illustrate the combinational logic circuit, in which the combinational logic circuit is composed of a D flip-flop, a NOT gate, an AND gate, and an OR gate. In the combinational logic circuit, the clock input to the first input terminal is delayed and aligned according to the clock S1 input to the second input terminal, so that the falling edge of the clock after the delay alignment is the same as the falling edge of the clock S1. Then, the clock S1 and the clock after the delay alignment are ANDed to obtain the clock S3. Then, the clock Φ can be obtained by appropriately delaying the clock S3. 12 . Set the clock S3 and clock Φ 12 Perform an AND operation and invert it, then delay the inverted clock appropriately to get Φ 11 Based on the operation of appropriate delay, Φ 11 and Φ 12 There is no time when both are high at the same time. The implementation of the combinational logic circuit is not limited here, as long as it can achieve the same effect as this example.

[0061] See also Figure 4 , Figure 4 is a schematic diagram of the structure of an integrator provided by an embodiment of the present invention. The integrator includes a switched capacitor network, an adjustable capacitor array, a differential operational amplifier, and a CLS network. CM Indicates the common-mode voltage.

[0062] The switch capacitor network mainly includes a sampling capacitor C1, a sampling capacitor C2, an integrating capacitor C3, an integrating capacitor C4, a gate voltage bootstrap switch K1, a gate voltage bootstrap switch K2, and a CMOS switch K3-CMOS switch K8. The switch capacitor network in the embodiment of the present invention is described in detail below, wherein the switch capacitor network includes a first switch capacitor network and a second switch capacitor network.

[0063] The first switch capacitor network includes: sampling capacitor C1, integration capacitor C3, gate voltage bootstrap switch K1, CMOS switch K3, CMOS switch K5 and CMOS switch K7. The connection relationship is as follows: the first end of the gate voltage bootstrap switch K1 is connected to the positive electrode, the second end of the gate voltage bootstrap switch K1 is connected to the first end of the sampling capacitor C1, the first end of the CMOS switch K3 is connected to the common mode voltage, the second end of the CMOS switch K3 is connected to the first end of the sampling capacitor C1, the second end of the sampling capacitor C1 is connected to the first end of the CMOS switch K7, the first end of the CMOS switch K5 is connected to the common mode voltage, the second end of the CMOS switch K5 is connected to the second end of the sampling capacitor C1, the second end of the CMOS switch K7 outputs a positive sampling signal, the first end of the integration capacitor C3 is connected to the positive sampling signal, the second end of the integration capacitor C3 is connected to the first output end of the CLS network, and outputs a positive integration signal.

[0064] The second switch capacitor network includes: sampling capacitor C2, integration capacitor C4, gate voltage bootstrap switch K2, CMOS switch K4, CMOS switch K6 and CMOS switch K8. The connection relationship is as follows: the first end of the gate voltage bootstrap switch K2 is connected to the negative electrode, the second end of the gate voltage bootstrap switch K2 is connected to the first end of the sampling capacitor C2, the first end of the CMOS switch K4 is connected to the common mode voltage, the second end of the CMOS switch K4 is connected to the first end of the sampling capacitor C2, the second end of the sampling capacitor C2 is connected to the first end of the CMOS switch K8, the first end of the CMOS switch K6 is connected to the common mode voltage, the second end of the CMOS switch K6 is connected to the second end of the sampling capacitor C2, the second end of the CMOS switch K8 outputs a negative sampling signal, the first end of the integration capacitor C4 is connected to the negative sampling signal, the second end of the integration capacitor C4 is connected to the second output end of the CLS network, and outputs a negative integration signal.

[0065] The gate voltage bootstrap switch is a power electronic switch with the characteristics of fast switching speed and low loss. Figure 5 , Figure 5It is a schematic diagram of the structure of the gate voltage bootstrap switch provided by an embodiment of the present invention. The gate voltage bootstrap switch is composed of 11 MOS tubes, namely M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, and a capacitor C9. In the gate voltage bootstrap switch, CLK represents the clock generated by the received clock control circuit, and NCLK is the non-signal of the CLK signal. When CLK is high, the switch is turned on, that is, the switch is closed. VDD represents the power supply voltage. GND represents grounding. IN is the input end of the gate voltage bootstrap switch, and OUT is the output end of the gate voltage bootstrap switch.

[0066] In the embodiment of the present invention, switches K3-K8 are CMOS transmission gates formed by complementary PMOS and NMOS. Figure 6 , Figure 6 : is a schematic diagram of the structure of a CMOS switch provided by an embodiment of the present invention. The CMOS switch is composed of two MOS transistors M18 and M19. In the CMOS switch, IN is the input end of the CMOS switch, OUT is the output end of the CMOS switch, CLK represents the clock generated by the received clock control circuit, and NCLK is the non-signal of the CLK signal.

[0067] In the embodiment of the present invention, the switches K1 and K2 are gate voltage bootstrap switches to ensure the accuracy of signal sampling, and the other switches are CMOS switches to reduce the complexity of the overall circuit.

[0068] Take the first switch capacitor network as an example for analysis, combined with Figure 3 and Figure 4 It can be seen that the clock S 2D Control switch K1, clock S 1D Control switch K3, clock S2 controls switch K5, and clock S1 controls switch K7. 2D At high level, switches K1 and K5 are closed, and the signal sampled from the negative electrode is sampled to the sampling capacitor C1. Then S2 and S 2D At low level, switches K1 and K5 are disconnected, S1 and S 1D At a high level, switches K3 and K7 are closed, and the charge on the sampling capacitor C1 is transferred to the integration capacitor C3 through the virtual short effect of the differential operational amplifier input terminal. This charge transfer process integrates the negative sampling signal and finally outputs the negative integration signal. The sampling and integration process of the second switch capacitor network is similar.

[0069] See also Figure 4 In the embodiment of the present invention, the CLS network includes capacitor C7, capacitor C8 and switches K9-K14.

[0070] In the embodiment of the present invention, the CLS network includes a first CLS sub-network and a second CLS sub-network.

[0071] The first CLS sub-network includes a switch K9, a switch K11, a switch K13 and a capacitor C7. The connection relationship is as follows: the first end of the switch K9 is connected to the common mode voltage, the second end of the switch K9 is connected to the first end of the capacitor C7, the first end of the switch K11 is connected to the first differential amplified signal, the second end of the switch K11 is connected to the first end of the capacitor C7, the first end of the switch K13 is connected to the first differential amplified signal, the second end of the switch K13 is connected to the second end of the capacitor C7, and the second end of the capacitor C7 is connected to the positive electrode integrated signal.

[0072] The second CLS sub-network includes a switch K10, a switch K12, a switch K14 and a capacitor C8. The connection relationship is as follows: the first end of the switch K10 is connected to the common mode voltage, the second end of the switch K10 is connected to the first end of the capacitor C8, the first end of the switch K12 is connected to the second differential amplified signal, the second end of the switch K12 is connected to the first end of the capacitor C8, the first end of the switch K14 is connected to the second differential amplified signal, the second end of the switch K14 is connected to the second end of the capacitor C8, and the second end of the capacitor C8 is connected to the negative electrode integrated signal.

[0073] In the embodiment of the present invention, based on the CLS network, the virtual short effect generated by the differential operational amplifier can be optimized, and the optimized virtual short effect is equivalent to improving the equivalent gain of the differential operational amplifier.

[0074] Specifically, the output value of the differential operational amplifier is equal to the input value of the differential operational amplifier multiplied by the gain of the differential operational amplifier. In an ideal case, the gain of the differential operational amplifier is approximately considered to be infinite. By inverse deduction, the input voltage of the differential operational amplifier is equal to the output value of the differential operational amplifier divided by the gain of the differential operational amplifier. The output value of the differential operational amplifier is a finite value, and the gain is infinite in an ideal case, so the input of the differential operational amplifier is zero in an ideal case. However, in actual cases, the gain of the differential operational amplifier is a large value, so the input of the differential operational amplifier is a value approximately equal to zero. This phenomenon is the virtual short effect of the differential operational amplifier. Based on this, it can be seen that in order to increase the gain of the differential operational amplifier, the differential operational amplifier needs to obtain a better virtual short effect.

[0075] Take the first CLS sub-network as an example for analysis. Figure 3 and Figure 4 It can be seen that the clock Φ 11 Control switch K9 and switch K13, clock Φ 12 Control switch K11. First, clock Φ 11At a high level, switches K9 and K13 are closed, and one end of capacitor C7 is connected to the output of the first switch capacitor network, and the other end is connected to the common mode voltage through the closed switch K9. After that, switches K9 and K13 are disconnected, and clock Φ 12 At a high level, switch K11 is closed, and one end of capacitor C7 is still connected to the output of the first switch capacitor network, while the end originally connected to the common mode voltage is now connected to the output of the differential operational amplifier. Assuming that the voltage on capacitor C7 does not change, and the second CLS network can be analyzed in the same way, then at this time, the voltage values ​​of the two output ends of the differential operational amplifier are both common mode voltages. Therefore, the differential output value of the differential operational amplifier approaches 0, and according to the input-output relationship of the differential operational amplifier, the differential input value of the differential operational amplifier also approaches 0.

[0076] Therefore, the embodiment of the present invention can achieve a better virtual short effect for the differential operational amplifier through the CLS network, thereby improving the gain of the differential operational amplifier and alleviating the integration error of the positive integral signal and the negative integral signal. However, charge sharing occurs between the capacitors in the CLS network and the capacitors in the switched capacitor network, limiting the integration accuracy. In order to solve this problem, the embodiment of the present invention provides an adjustable capacitor array including a first adjustable capacitor subarray and a second adjustable capacitor subarray.

[0077] In the embodiment of the present invention, the first adjustable capacitor sub-array and the second adjustable capacitor sub-array are both binary code capacitor arrays or thermometer code capacitor arrays. Figure 7 , Figure 7 1 is a schematic diagram of the structure of a binary code capacitor array provided by an embodiment of the present invention. The binary code capacitor array is composed of 8-bit binary codes, specifically including 16 switches, namely switch K <a1>, switch K <a2>...Switch K <a16>And 8 capacitors, namely capacitor C <a1> 、C <a2> ……C <a8>.

[0078] Because the optimal size of the capacitor array is related to the size of the sampling capacitor and the integrating capacitor and the gain of the differential operational amplifier, in order to prevent the compensation effect of the capacitor array from being affected by the gain of the differential operational amplifier, it is necessary to ensure that the capacitor array has a large adjustable range. The upper and lower plates of each capacitor in the capacitor array are connected to the switch to determine whether to connect to the entire circuit. Since the switch has little effect on the overall circuit, the switch here uses a simple CMOS switch. For example, if you only want to connect capacitor C <a1>With C <a2>When the switch K is closed <a1> 、K <a2> 、K <a9> 、K <a10>, disconnect the remaining switches.

[0079] In an embodiment of the present invention, the capacitance of the first adjustable capacitor array is smaller than the capacitance of the integral capacitor in the first switched capacitor network; the capacitance of the second adjustable capacitor array is smaller than the capacitance of the integral capacitor in the second switched capacitor network. Since the two ends of the adjustable capacitor array are connected to the in-phase port of the differential operational amplifier, in order to ensure the stability of the overall integrator, the capacitance of the adjustable capacitor array is much smaller than the capacitance of the integral capacitor in the switched capacitor network. This connection method can utilize the Miller effect to make the adjustable capacitor array equivalent to a negative capacitor at the input end of the differential operational amplifier, thereby avoiding charge sharing between the capacitor in the switched capacitor network and the capacitor in the CLS network, and effectively improving the accuracy of the circuit.

[0080] In the embodiment of the present invention, the differential operational amplifier may be a fully differential inverter type operational amplifier, see Figure 8 , Figure 8 1 is a schematic diagram of the structure of a fully differential inverter operational amplifier provided by an embodiment of the present invention. The fully differential inverter operational amplifier includes 6 MOS transistors, namely M1, M2, ..., M6. The two output ends of the fully differential inverter operational amplifier are connected to a CMFB (common mode feedback module), and the bias voltage V required by M1 and M6 can be generated by CMFB. CMFB . Among them, OUT P Indicates positive output, OUT N Indicates the negative output.

[0081] Based on the same inventive concept, an embodiment of the present invention further provides a sigma delta analog-to-digital converter, which includes any one of the above-mentioned high-precision switched capacitor integration circuits.

[0082] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0083] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0084] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0085] In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connection", etc. should be understood in a broad sense, for example, it can be a direct electrical connection, or it can be an indirect electrical connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention. < / a9> < / a2> < / a1> < / a2> < / a1>

Claims

1. A high-precision switched capacitor integration circuit based on negative capacitance assisted CLS technology, characterized in that: The high-precision switched capacitor integration circuit includes a clock control circuit, a switched capacitor network, an adjustable capacitor array, a differential operational amplifier and a CLS network; The clock control circuit is used to generate a two-phase non-overlapping clock and a CLS clock; the CLS clock is used to control the switching of switches in the CLS network; The switch capacitor network is used to sample the positive and negative electrodes of the input terminal under the control of the two-phase non-overlapping clock to obtain a positive sampling signal and a negative sampling signal; integrate the positive sampling signal and the negative sampling signal to output a positive integrated signal and a negative integrated signal; The differential operational amplifier is used to transfer the charge on the sampling capacitor in the switched capacitor network to the integrating capacitor when integrating the positive sampling signal and the negative sampling signal in the switched capacitor network, and output a first differential amplified signal and a second differential amplified signal; The CLS network has one end connected to the first differential amplified signal and the second differential amplified signal, and the other end connected to the positive electrode integral signal and the negative electrode integral signal, and the CLS network is used to perform relevant level shift on the first differential amplified signal and the second differential amplified signal under the control of the CLS clock to alleviate the integral error of the positive electrode integral signal and the negative electrode integral signal; The adjustable capacitor array comprises a first adjustable capacitor subarray and a second adjustable capacitor subarray; one end of the first adjustable capacitor subarray is connected to the inverting input end of the differential operational amplifier, and the other end is connected to the inverting output end of the differential operational amplifier; one end of the second adjustable capacitor subarray is connected to the non-inverting input end of the operational amplifier, and the other end is connected to the non-inverting output end of the operational amplifier.

2. The high-precision switched capacitor integration circuit according to claim 1, characterized in that: The clock control circuit includes a buffer, a frequency divider, a two-phase non-overlapping clock module and a combinational logic circuit; The input end of the buffer is connected to the external clock, the first output end of the buffer is connected to the input end of the frequency divider, the second output end of the buffer is connected to the first input end of the combinational logic circuit, the output end of the frequency divider is connected to the input end of the two-phase non-overlapping clock module, the first output end of the two-phase non-overlapping module outputs the two-phase non-overlapping clock, the second output end of the two-phase non-overlapping module is connected to the second input end of the combinational logic circuit, and the combinational logic circuit is used to perform a logical combination operation on the clock received at its second input end and the clock received at its first input end to output the CLS clock; the CLS clock includes no clocks Φ that are simultaneously at a high level 11 and clock Φ 12 The two-phase non-overlapping clock module is used to perform two-phase non-overlapping clock processing on the input clock to obtain a two-phase non-overlapping clock; the two-phase non-overlapping clock includes a clock S1 and a clock S2 that do not have a high level at the same time and a delayed signal S of the clock S1. 1D and the delayed signal S of the clock S2 2D .

3. The high-precision switched capacitor integration circuit according to claim 1, characterized in that: The switched capacitor network includes a first switched capacitor network and a second switched capacitor network; The first switch capacitor network includes: a sampling capacitor C1, an integrating capacitor C3, a gate voltage bootstrap switch K1, a CMOS switch K3, a CMOS switch K5 and a CMOS switch K7; The first end of the gate voltage bootstrap switch K1 is connected to the positive electrode, the second end of the gate voltage bootstrap switch K1 is connected to the first end of the sampling capacitor C1, the first end of the CMOS switch K3 is connected to the common mode voltage, the second end of the CMOS switch K3 is connected to the first end of the sampling capacitor C1, the second end of the sampling capacitor C1 is connected to the first end of the CMOS switch K7, the first end of the CMOS switch K5 is connected to the common mode voltage, the second end of the CMOS switch K5 is connected to the second end of the sampling capacitor C1, the second end of the CMOS switch K7 outputs the positive electrode sampling signal, the first end of the integration capacitor C3 is connected to the positive electrode sampling signal, the second end of the integration capacitor C3 is connected to the first output end of the CLS network, and outputs the positive electrode integration signal; The second switch capacitor network includes a sampling capacitor C2, an integrating capacitor C4, a gate voltage bootstrap switch K2, a CMOS switch K4, a CMOS switch K6 and a CMOS switch K8; The first end of the gate voltage bootstrap switch K2 is connected to the negative electrode, the second end of the gate voltage bootstrap switch K2 is connected to the first end of the sampling capacitor C2, the first end of the CMOS switch K4 is connected to the common mode voltage, the second end of the CMOS switch K4 is connected to the first end of the sampling capacitor C2, the second end of the sampling capacitor C2 is connected to the first end of the CMOS switch K8, the first end of the CMOS switch K6 is connected to the common mode voltage, the second end of the CMOS switch K6 is connected to the second end of the sampling capacitor C2, the second end of the CMOS switch K8 outputs the negative electrode sampling signal, the first end of the integration capacitor C4 is connected to the negative electrode sampling signal, the second end of the integration capacitor C4 is connected to the second output end of the CLS network, and outputs the negative electrode integration signal.

4. The high-precision switched capacitor integration circuit according to claim 3, characterized in that: The CLS network includes a first CLS sub-network and a second CLS sub-network; The first CLS sub-network includes a switch K9, a switch K11, a switch K13 and a capacitor C7; The first end of the switch K9 is connected to the common mode voltage, the second end of the switch K9 is connected to the first end of the capacitor C7, the first end of the switch K11 is connected to the first differential amplified signal, the second end of the switch K11 is connected to the first end of the capacitor C7, the first end of the switch K13 is connected to the first differential amplified signal, the second end of the switch K13 is connected to the second end of the capacitor C7, and the second end of the capacitor C7 is connected to the positive electrode integrated signal; The second CLS sub-network includes a switch K10, a switch K12, a switch K14 and a capacitor C8; The first end of the switch K10 is connected to the common mode voltage, the second end of the switch K10 is connected to the first end of the capacitor C8, the first end of the switch K12 is connected to the second differential amplified signal, the second end of the switch K12 is connected to the first end of the capacitor C8, the first end of the switch K14 is connected to the second differential amplified signal, the second end of the switch K14 is connected to the second end of the capacitor C8, and the second end of the capacitor C8 is connected to the negative electrode integrated signal.

5. The high-precision switched capacitor integration circuit according to claim 1, characterized in that: The capacitance of the first adjustable capacitor array is smaller than the capacitance of the integral capacitor in the first switched capacitor network; the capacitance of the second adjustable capacitor array is smaller than the capacitance of the integral capacitor in the second switched capacitor network.

6. The high-precision switched capacitor integration circuit according to claim 1, characterized in that: The first adjustable capacitor subarray and the second adjustable capacitor subarray are both binary code capacitor arrays or thermometer code capacitor arrays.

7. The high-precision switched capacitor integration circuit according to claim 1, characterized in that: The differential operational amplifier is a fully differential inverter type operational amplifier.

8. A sigma delta analog-to-digital converter, characterized in that: The invention comprises a high-precision switched capacitor integration circuit as described in any one of claims 1 to 7.

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