The invention discloses a method for designing an embedded, isomorphic, symmetric and dual-core microprocessor, which forms inner core units by module division according to the relative independency of an instruction fetch unit, a decoding unit, a control unit and a data path internal logistic module, designs a 32-bit dual-core RISC micro structure by using internal modules of a 32-bit RISC micro structure as an IP and expanding functions according to requirements, realizes the synchronization in terms of dual-core instruction fetch and avoids repeated instruction fetch of the two cores or instruction fetch omission by adopting a common PC register proposal, simplifies design by using a policy of sequential emission, namely executing according to the instruction fetch sequences of the two cores, designs a shared register file proposal according to data exchange between the two cores to allow the two cores to share resources, improve data exchange flexibility, avoid realizing data sharing by expanding an instruction set and reduce design period, and adopts a policy of assembly line control combination to realize unified management of two assembly lines and operational coordination of the two assembly lines.