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108results about How to "Number of Eliminations" patented technology

Graphene fet devices, systems, and methods of using the same for sequencing nucleic acids

Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. Accordingly, GFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis within a gated reaction chamber of the GFET based sensor.
Owner:CARDEA BIO INC

Method for shortening the resynchronization time following failure in a computer system utilizing separate servers for redundancy

ActiveUS7246255B1Efficient system recoveryMinimum computing timeDigital data information retrievalProgram synchronisationMass storageServer replication
An apparatus for and method of enhancing reliability within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are managed by a cluster lock manager. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster / lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster / locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster / lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system. Furthermore, the recovery is completely accomplished without assistance of the Host computer(s) or ultimate user(s) coupled via the Host computer(s). Following repair of the failed server, it is restarted in an orderly fashion to resume a slave role. For the server to be completely restored, coherent memory must be copied from master to slave. Because cluster lock processing must be paused throughout the system to transfer the copy, it is important to minimize the transfer time to minimize the impact on system throughput.
Owner:UNISYS CORP
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