Modeling method of microwave device model applied to flip-chip integration

Abstract

The invention discloses a modeling method for a microwave device model applied to flip integration. The method comprises the following steps: designing and manufacturing a bonding pad on the surface of a bare chip of a microwave device and an input and output structure for on-chip probe testing; the ball bumps are attached to the bonding pads, metal or dielectric cover plates are welded to the tops of the ball bumps, the working environment of the flip-chip microwave device is simulated, and a to-be-tested piece applied to the flip-chip integrated microwave device is obtained; obtaining the direct current and radio frequency characteristics of the inverted microwave device; designing a de-embedding structure and simulating radio frequency characteristics, and performing de-embedding processing on the radio frequency characteristics of the inverted microwave device; and based on the equivalent circuit model topological structure, establishing an inverted microwave device model containing set sum distribution network parameters at the same time, comparing simulation data of the inverted microwave device with test data, and verifying the accuracy of the inverted microwave device model. The method can be used for modeling the inverted integrated microwave device model simply, conveniently, efficiently and accurately.

Description

Technical Field

[0001] The invention relates to the technical field of microwave device modeling, and in particular to a microwave device modeling method applied to flip-chip integration. Background Art

[0002] Flip chip integration is a chip integration packaging method that directly interconnects the front pads of the chip to the metal pad layer of the adapter board, substrate or circuit board through ball bumps or copper pillar bumps to achieve input / output interconnection. Compared with the traditional front-mounted integration in which the chip is bonded on the back and the front pads of the chip are interconnected by wire bonding, its significant difference is that the front of the chip and the carrier are face-to-face, and ball bumps or copper pillar bumps are used instead of wire bonding for interconnection, so it is also called flip chip bonding. Flip chip integration is gradually becoming one of the important ways of efficient interconnection and integration packaging of monolithic microwave integrated circuits (MMICs) with its performance advantages such as low loss, high integration and high reliability.

[0003] Flip-chip integration has changed the traditional wire-bonded integration form. The electromagnetic field distribution on the surface of the microwave chip circuit will be limited by the morphology and boundaries of the air or dielectric cavity (dielectric filling) formed after flipping, which is different from the electromagnetic field distribution in the relatively open air cavity environment when the chip is mounted (the cavity height when mounted is usually several times the thickness of the substrate, while the cavity height of the flip-chip is equivalent to or smaller than the thickness of the substrate). Therefore, the characteristic impedance, parasitic parameters and other characteristics of the components in the microwave chip will change due to flip-chip integration, which will cause a certain frequency band shift and ultimately affect the RF performance of the microwave circuit. Therefore, in order to achieve high-precision microwave chip circuit design simulation and optimization for flip-chip integration, it is necessary to carry out targeted modeling of the components of the flip-chip.

[0004] Although a large number of literature reports have been published on the process of flip-chip integration, there are few reports on the modeling methods for flip-chip microwave devices. Therefore, in order to meet the development requirements of microwave flip-chip integration process technology and meet the needs of high-precision simulation design and optimization of flip-chip circuits, it is urgent to study the modeling methods of microwave devices applied to flip-chip integration. Summary of the invention

[0005] The main purpose of the present invention is to propose a microwave device modeling method for flip-chip integration to achieve simple, efficient and accurate flip-chip device modeling, in order to address the problem that chip circuit simulation design used for flip-chip integration lacks a special high-precision model of flip-chip devices, and that the traditional face-mounted device model simulation design is prone to characteristic differences such as frequency band offset.

[0006] The present invention discloses a microwave device modeling method for flip-chip integration, which comprises:

[0007] Step 1: Design and manufacture pads on the surface of the microwave device die, as well as input and output structures for on-wafer probe testing;

[0008] Step 2: attaching the ball bumps to the pads, and welding a metal or dielectric cover plate on top of the ball bumps to cover the effective area of ​​the entire device, simulating the working environment of the flip-chip microwave device, and obtaining a test piece for the microwave device applied to flip-chip integration;

[0009] Step 3: testing the DUT with an on-chip probe to obtain the DC and RF characteristics of the flip-chip microwave device;

[0010] Step 4: Design a de-embedding structure and simulate the RF characteristics to de-embed the RF characteristics of the flip-chip microwave device;

[0011] Step 5: Based on the topological structure of the equivalent circuit model, a device model including both lumped and distributed network parameters is established, and the simulation data of the flipped microwave device model is compared with the test data obtained in steps 3 and 4 to verify the accuracy of the flipped microwave device model.

[0012] Furthermore, the step 1 comprises:

[0013] The input-output structure is a transmission structure with a "ground-signal-ground" (GSG) pad and a connecting line, and is connected to the input and output ports of the device to form an on-wafer probe test structure; a power tube core transistor microwave device is designed on a substrate; the connecting line is a microstrip transmission line; the grounding back hole is located under the grounding pad, the back hole height is consistent with the substrate thickness, and is distributed on both sides of the input and output end connecting line; the back side of the substrate is a whole back gold layer, which is connected to the back hole and grounded.

[0014] Furthermore, the pad size of the welding bump in the pad is equivalent to the bump diameter, and is located on the upper and lower sides of the device, respectively. Multiple bump pads of the same size are distributed on each side and are spaced a preset distance from the center of the device. The pad and the input and output transmission lines of the device need to be spaced apart to reduce the transmission parasitic coupling effect of the bump. At the same time, a back hole structure is designed at the edge of each bump pad to connect it.

[0015] Furthermore, the step 2 comprises:

[0016] A gold wire ultrasonic hot-compression bonding process is adopted to plant multiple gold ball bumps on the pads used for ball planting. The ultrasonic power, pressure, current and time are controlled to ensure that the diameter and height of each gold ball are consistent. A metal cover plate or a dielectric cover plate is welded on the top of the gold ball by ultrasonic hot-compression welding. The size of the metal cover plate or the dielectric cover plate can cover the size area of ​​the transistor device to ensure that the working state of the transistor is consistent with the real flip-chip device integrated electromagnetic environment. A pad is provided on the surface of the substrate for bump welding to simulate the real cavity electromagnetic environment when the flip-chip device is working.

[0017] Furthermore, the step 3 comprises:

[0018] An on-wafer test bench is used to test the current-voltage curve with an on-wafer probe. The multi-bias small signal scattering parameter characteristics are measured, and the voltage bias is consistent with the IV curve scanning bias point. The source and drain loads are pulled, and the operating frequency and the input power of the saturated working state are set respectively. The maximum output power and maximum power added efficiency of the device are pulled respectively, and the RF characteristics of the flip-chip microwave device are scanned, including the equal power and equal efficiency circle diagrams and the harmonic distortion characteristics.

[0019] Furthermore, the step 4 comprises:

[0020] Electromagnetic simulation software is used to design the de-embedding structure, and electromagnetic simulation is performed on the open and short-circuit de-embedding structures; the open and short-circuit de-embedding structures also include bumps and covers, simulating the open and short-circuit RF characteristics of the flip-chip integration environment.

[0021] Furthermore, the step 4 comprises:

[0022] The S parameters measured by the DUT are converted into admittance parameters (Y parameters), and the open circuit and short circuit de-embedding structures are established in the electromagnetic simulation software. The electromagnetic simulation simulates the S parameter characteristics of the open circuit and short circuit structures, obtains the open circuit structure S parameters and the short circuit structure S parameters, and converts them into Y parameters respectively. The Y parameters include the open circuit admittance parameters and the short circuit admittance parameters. First, the capacitance effect of the probe pad is removed, that is, the open circuit admittance parameter after removing Yopen is equal to the admittance parameter of the DUT minus Yopen, Ym_open=Ym-Yopen, and the calculated result Ym_open is converted into an impedance parameter, that is, a Z parameter; wherein Yopen and Yshort are the open circuit admittance parameter and the short circuit admittance parameter respectively; Ym_open is the open circuit admittance parameter after removing Yopen; Ym is the admittance parameter of the DUT; and Zm_open is the impedance parameter;

[0023] Secondly, remove the capacitive effect of the short-circuit structure, that is, remove the admittance parameter of the short-circuit structure after Yopen is removed, Yshort_open=Yshort-Yopen, and convert the calculated result Yshort_open into a Z parameter, which is recorded as Zm_short_open; then deduct the resistance and inductance effects of the DUT to obtain the impedance parameter Zd=Zm_open-Zm_short_open; finally, convert Zd into an S parameter, that is, obtain the S parameter test result after the DUT is de-embedded.

[0024] Furthermore, in order to utilize the RF S parameter characteristics of the open and short circuit de-embedded structures, the optimal source impedance of the de-embedded flip-chip microwave device is obtained, so as to realize the influence of the de-embedded test pads and connecting wires and obtain the performance of the flip-chip microwave device itself.

[0025] Furthermore, the step 5 comprises:

[0026] According to the test data and the topological structure of the equivalent circuit model, the parameter values ​​of each component in the flip-chip microwave device model are determined by using the model parameter extraction method;

[0027] The established flip-chip microwave device model is simulated and verified, and the fitting accuracy of the test and simulation results is compared to complete the model simulation verification; the performance includes DC IV curve, small signal S parameters, noise parameters, large signal output power and intermodulation characteristics.

[0028] Furthermore, the topological structure of the equivalent circuit model includes three ports of gate G, drain D and source S, as well as an external parasitic parameter network and an internal intrinsic parameter network. The parasitic parameter network describes the parasitic coupling effect between the device and the substrate, the flip-chip air cavity or the dielectric cavity, and is composed of lumped parameter and distributed parameter networks; the lumped parameters include parasitic capacitance element Cp1, parasitic capacitance element Cp2 and parasitic capacitance element Cp12, parasitic resistance element R1, parasitic resistance element R2 and parasitic resistance element R3, and the distributed parameter network includes transmission line line1, transmission line line2 and transmission line line3; the intrinsic parameters include gate junction capacitance C1, gate junction capacitance C2 and drain-source capacitance C3, gate diodes D1 and D2, and channel nonlinear current source I1;

[0029] The gate G is connected to the transmission line line1, the gate junction capacitor C2, the transmission line line2, the parasitic resistance element R2 and the drain D in sequence through the parasitic resistance element R1; the source S is connected to the transmission line line3 through the parasitic resistance element R3; the gate diode D1 is connected in parallel with the gate junction capacitor C1, one end of the gate junction capacitor C1 is connected to the transmission line line3, and the other end is connected to one end of the gate junction capacitor C2; the channel nonlinear current source I1 is connected in parallel with the gate junction capacitor C3, one end of the gate junction capacitor C3 is connected to the transmission line line3, and the other end is connected to the gate junction capacitor C2 The other end of the gate is connected; the gate diode D2 is connected in parallel with the gate junction capacitance C2; ​​the parasitic capacitance element Cp1, the parasitic capacitance element Cp2 and the parasitic capacitance element Cp12 are connected in sequence; the common end of the parasitic capacitance element Cp1 and the parasitic capacitance element Cp2 is the same as the common end of the gate G and the parasitic resistance element R1; the common end of the parasitic capacitance element Cp1 and the parasitic capacitance element Cp2 is the same as the common end of the gate S and the parasitic resistance element R3; the common end of the parasitic capacitance element Cp2 and the parasitic capacitance element Cp12 is the same as the common end of the gate D and the parasitic resistance element R2.

[0030] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0031] 1) The present invention directly plants balls and welds capping layers on the bare chip of the microwave device, simulating the working environment of a real flip-chip microwave device. There is no need to manufacture flip-chip devices on other carriers. The modeled test piece is easy to manufacture and obtain.

[0032] 2) The DUT of the present invention can be directly probed and de-embedded on-wafer without introducing an additional flip-chip carrier and the RF characteristics of the corresponding de-embedded structure, making it easy to obtain high-precision on-wafer test data with smaller de-embedded error.

[0033] 3) The present invention adopts both lumped and distributed parameter networks to describe the parasitic coupling effect of the flip-chip microwave device, which is more physically meaningful and has a higher model accuracy than the traditional lumped equivalent circuit.

[0034] 4) The present invention is based on a modeling method for ball implantation and solder capping on a microwave device bare chip, and can be used for modeling flip chips of different processes. It has a wide range of applications and can meet the requirements of modifying model parameters without changing the modeling method according to different flip chip integration process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0036] Figure 1 A schematic diagram of the structure of a DUT simulating a flip chip environment according to an embodiment of the present invention;

[0037] FIG2( a ) is a schematic diagram of an open circuit de-embedding structure of a device under test according to an embodiment of the present invention;

[0038] FIG2( b ) is a schematic diagram of a short circuit de-embedding structure of a device under test according to an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the topological structure of an equivalent circuit model of a flip-chip microwave device according to an embodiment of the present invention;

[0040] FIG4( a ) is a simulation result of the input reflection coefficient in the S parameter of the flip-chip microwave device model according to an embodiment of the present invention;

[0041] FIG4( b ) is a simulation result of the reverse transmission coefficient of an embodiment of the present invention;

[0042] FIG4( c ) is a simulation result of the forward transmission coefficient of an embodiment of the present invention;

[0043] FIG4( d ) is a simulation result of the output reflection coefficient of an embodiment of the present invention;

[0044] FIG4( e ) is a simulation result of output power, efficiency and gain of an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in conjunction with the accompanying drawings and embodiments, and the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present invention.

[0046] The present invention provides a microwave device modeling method for flip-chip integration, comprising the following steps:

[0047] Step S1: Design and manufacture pads capable of receiving ball bumps and input and output structures capable of on-chip probe testing on the surface of a microwave device die.

[0048] In this step, the standard component layout provided by the wafer foundry is used to draw device layout graphics and structure layout graphics that can be tested on the wafer, as well as pads for ball bumping. Figure 1 FIG. 1 is a schematic diagram of the structure layout of the DUT simulating the flip chip environment of the present embodiment.

[0049] Among them, microwave device types include active and passive devices, such as inductors, resistors, capacitors, transmission lines and transistor devices, and the device materials are silicon, gallium arsenide, gallium nitride, etc. The input and output structure is a transmission structure with GSG pads and connecting wires, and is connected to the input and output ports of the device to form an on-wafer probe test structure layout. Taking the typical GaAs pHEMT manufacturing process as an example, a power tube core transistor microwave device is designed on a GaAs substrate 1 with a thickness of 150 microns. The total gate width of the device tube core 2 is 900 microns (including 6 gate fingers, and the unit gate finger width is 150 microns); the connecting line is a microstrip transmission line 3 with a length of 400 microns and a width of 70 microns; the input and output GSG pads 4 are square structures with a side length of 100 microns, and the center spacing of the pads is 150 microns. The grounding back hole 5 is located under the grounding pad. The height of the back hole is consistent with the thickness of the GaAs substrate, which is 150 microns, and is distributed on both sides of the input and output connecting line 3; the back side of the substrate 1 is a whole back gold layer 6, which is connected to the back hole and forms a good grounding.

[0050] In addition, the pad size of the solder bump in the pad 7 for ball planting is equivalent to the bump diameter, and can be selected to be the same size as the GSG pad, that is, the side length is 100 microns, and is located on the upper and lower sides of the device (with the left and right as the input and output ends), respectively, with two bump pads of the same size distributed on each side, and the distance from the center of the device is about 300 microns. It should be noted that the pad and the input and output transmission lines of the device need to maintain a certain interval to reduce the transmission parasitic coupling effect of the bump, and at the same time, a back hole structure 5 is designed at the edge of each bump pad to connect with it, so that it has a good grounding effect.

[0051] Step S2: placing ball bumps on the pads for ball planting, and welding a metal or dielectric cover plate on top of the ball bumps to cover the entire effective area of ​​the device, simulating the working environment of the flip-chip microwave device, and obtaining a microwave device to be tested for flip-chip integration.

[0052] After the step S1 is completed, four gold ball bumps 8 are planted on the pads 7 for ball planting. The ball planting method adopts the gold wire ultrasonic hot pressing bonding process. The gold wire diameter is selected to be 1mil, and the ball bump diameter is about 80um. Control the ultrasonic power, pressure, current and time to ensure the consistency of the diameter and height of each gold ball. The detailed setting of the ultrasonic parameters depends on the specific ultrasonic equipment. Subsequently, a metal cover plate or a dielectric cover plate 9 is welded on the top of the gold ball by ultrasonic hot pressing. The length and width of the cover plate are 1.2mm and 0.7mm respectively. The size of the cover plate can cover more than 3 to 5 times the size area of ​​the transistor device to ensure that the working state of the transistor is consistent with the real inverted microwave device integrated electromagnetic environment. The metal cover plate can use a double-sided copper-plated and gold-plated ceramic substrate, and the dielectric cover plate can use a silicon, composite substrate or other actual inverted integrated dielectric substrate. The substrate surface needs to have a pad for bump welding. This manufacturing structure is used to simulate the real cavity electromagnetic environment when the inverted microwave device is working.

[0053] Step S3: testing the DUT with an on-chip probe to obtain the DC and RF characteristics of the flip-chip microwave device.

[0054] Taking gallium arsenide pseudomorphic high electron mobility (GaAs pHEMT) transistor devices as an example, an on-wafer test bench and an on-wafer probe are used to test the current-voltage (IV) curve. The gate scanning range is Vg=-2V to +1.0V, with a step of 0.1V, and the drain scanning range is Vd=0V to 10V, with a step of 0.1V; the multi-bias small signal scattering parameter (S parameter) characteristics are measured, and the voltage bias is consistent with the IV curve scanning bias point, and the frequency range is 0.1GHz to 40GHz, with a step of 0.1GHz; the source and drain loads are pulled, and typical operating frequencies such as freq=5GHz, 10GHz, 20GHz, etc. are set respectively, and the input power (Pin) of the appropriate saturated working state is set, and the maximum output power and maximum power added efficiency of the device are pulled respectively, and the RF characteristics of the flip-chip microwave device are scanned, including the equal power and equal efficiency circle diagrams and the harmonic distortion (IM3) characteristics.

[0055] Step S4: designing a de-embedding structure and simulating radio frequency characteristics, and using microwave network theory to de-embed the radio frequency parameter characteristics of the flip-chip microwave device.

[0056] The RF characteristic data of the flip-chip microwave device measured and obtained in step S3 includes the characteristic influence of the probe pad and the connecting wire. In order to obtain the RF performance at the die, the test data needs to be de-embedded. Taking the de-embedded small signal S parameter characteristics as an example, the open circuit and short circuit structure method is usually used to complete the de-embedding. The de-embedding structure is designed using electromagnetic simulation software, and the designed de-embedding structure-the open / short circuit structure is subjected to electromagnetic simulation. Figure 2(a) is the open circuit de-embedding structure of the device under test, and Figure 2(b) is the short circuit de-embedding structure of the device under test. The de-embedding structure also includes bumps and a cover plate, simulating the open circuit and short circuit RF characteristics used in a flip-chip integrated environment.

[0057] The specific de-embedding method is as follows:

[0058] The S parameter (Sm) measured by the DUT is converted into a Y parameter (Ym), and the open / short circuit de-embedding structure shown in FIG2 is established in the electromagnetic simulation software. The electromagnetic simulation simulates the S parameter characteristics of the open circuit 10 in FIG2 (a) and the short circuit 11 in FIG2 (b), and the open circuit structure S parameter (Sopen) and the short circuit structure S parameter (Sshort) are obtained, and converted into Y parameters respectively. The Y parameters include the open circuit admittance parameter (Yopen) and the short circuit admittance parameter (Yshort). First, the capacitance effect of the probe pad is removed, that is, the open circuit admittance parameter (Ym_open) after removing Yopen is equal to the admittance parameter (Ym) of the DUT minus Yopen, Ym_open=Ym-Yopen, and the calculated result Ym_open is converted into an impedance parameter (Z parameter), that is, Zm_open. Secondly, remove the capacitance effect of the short-circuit structure, that is, remove the short-circuit structure admittance parameter Yshort_open = Yshort-Yopen after Yopen is removed, and convert the calculated result Yshort_open into a Z parameter, which is recorded as Zm_short_open; then deduct the resistance and inductance effects of the DUT to obtain the impedance parameter Zd = Zm_open-Zm_short_open. Finally, convert Zd into S parameters, that is, obtain the S parameter test result after the DUT is de-embedded.

[0059] Similarly, other RF characteristics of the flip-chip microwave device, such as noise parameters, optimal source and load impedance, etc., can be de-embedded through the RF characteristics of the open / short circuit de-embedding structure. Taking the load-pull impedance test as an example, the optimal source impedance of the test is Zs, or the optimal source reflection coefficient Гs. In order to de-embed the influence of the test pads and connecting wires and obtain the performance of the flip-chip microwave device itself, the RF S parameter characteristics of the open and short circuit de-embedding structure shown in Figure 2 are used, and combined with the following formula: Гs_de=S22+(S12*S21*Гs) / (1-S11*Гs) and the formula Zs_de=Z0*(1+Гs_de) / (1-Гs_de), the optimal source impedance Zs_de of the flip-chip microwave device after de-embedding can be obtained. Wherein, Гs_de is the source end reflection coefficient after de-embedding, Гs is the source end reflection coefficient before de-embedding, S11, S12, S21 and S22 are the input reflection coefficient, reverse transmission coefficient, forward transmission coefficient and output reflection coefficient of the de-embedding structure respectively, and Z0 is the characteristic impedance of 50 ohms.

[0060] Step S5, based on the equivalent circuit model topology, establish a flip-chip microwave device model that includes both lumped and distributed network parameters, and compare the model simulation data with the test data obtained in steps S3 and S4 to verify the accuracy of the model.

[0061] The equivalent circuit model topology of the flip-chip microwave device is as follows: Figure 3As shown, it includes three ports: gate G, drain D and source S. The topology includes an external parasitic parameter network and an internal intrinsic parameter network. The parasitic parameter network describes the parasitic coupling effect between the device and the substrate, the flip-chip air cavity or the dielectric cavity, and is composed of lumped parameter and distributed parameter networks. The lumped parameters include parasitic capacitance elements Cp1, Cp2 and Cp12, parasitic resistance elements R1, R2 and R3, and the distributed parameter network includes transmission lines line1, line2 and line3. Here, distributed parameters are used instead of traditional lumped parameters to describe its parasitic characteristics, making the flip-chip device model parameters more physically meaningful, and the extraction of intrinsic parameters is more accurate after stripping off the parasitic parameters. The intrinsic parameters include gate junction capacitance C1, C2 and drain-source capacitance C3, gate diodes D1 and D2, and channel nonlinear current source I1. According to the test data and the topology of the equivalent circuit model, the parameter values ​​of each component in the model can be determined by using the model parameter extraction method.

[0062] It is necessary to simulate and verify the established flip-chip microwave device model, compare the fitting accuracy of the test and simulation results, and simulate and verify the overall characteristics of the model, such as DC IV curve, small signal S parameters, noise parameters, large signal output power and intermodulation. Taking the flip-chip GaAs pHEMT device model as an example, the simulation results of its S parameters are shown in Figure 4(a), Figure 4(b), Figure 4(c), and Figure 4(d), respectively, and the output power, gain and efficiency simulation results of the flip-chip GaAs pHEMT device model are shown in Figure 4(e).

[0063] The above embodiments describe the implementation steps of the present invention in detail, but they cannot be understood as limiting the scope of the present invention. Based on the scope of the claims of the present invention, any form of change, replacement or modification made to the above embodiments does not deviate from the content of the present invention and is still within the protection scope of the present invention.

Claims

1. A microwave device modeling method for flip-chip integration, characterized in that: include: Step 1: Design and fabricate pads on the surface of the microwave device die, as well as input and output structures for on-wafer probe testing; Step 2: attaching ball bumps to the pads and welding a metal or dielectric cover plate on top of the ball bumps to cover the entire active area of ​​the device, simulating the working environment of a flip-chip microwave device, and obtaining a microwave device under test for flip-chip integration; Step 3: Testing the DUT with an on-wafer probe to obtain DC and RF characteristics of the flip-chip microwave device; Step 4: Design a de-embedding structure and simulate the RF characteristics to de-embed the RF characteristics of the flip-chip microwave device; Step 5: Based on the topological structure of the equivalent circuit model, a device model that includes both lumped and distributed network parameters is established, and the simulation data of the flip-chip microwave device model is compared with the test data obtained in steps 3 and 4 to verify the accuracy of the flip-chip microwave device model.

2. The method according to claim 1, characterized in that The step 1 comprises: The input-output structure is a transmission structure with pads and connecting lines, and is connected to the input and output ports of the device to form an on-wafer probe test structure; a power tube core transistor microwave device is designed on the substrate; the connecting line is a microstrip transmission line; the ground back hole is located under the ground pad, the back hole height is consistent with the substrate thickness, and is distributed on both sides of the input and output end connecting line; the back side of the substrate is a full-surface back gold layer, which is connected to the back hole and grounded.

3. The method according to claim 2, characterized in that The pad size of the solder bump in the pad is equivalent to the bump diameter. It is located on the upper and lower sides of the device, and multiple bump pads of the same size are distributed on each side. They are spaced a preset distance from the center of the device. The pad and the input and output transmission lines of the device need to be kept apart to reduce the parasitic coupling effect of the bump transmission. At the same time, a back hole structure is designed at the edge of each bump pad to connect it.

4. The method according to claim 1, wherein The step 2 includes: Using the gold wire ultrasonic hot-compression bonding process, multiple gold ball bumps are planted on the pads used for ball planting. The ultrasonic power, pressure, current and time are controlled to ensure that the diameter and height of each gold ball are consistent. Ultrasonic hot-compression welding is used to weld a metal cover or a dielectric cover on the top of the gold ball. The size of the metal cover or the dielectric cover can cover the size area of ​​the transistor device to ensure that the working state of the transistor is consistent with the real flip-chip device integrated electromagnetic environment; a pad is provided on the surface of the substrate for bump welding to simulate the real cavity electromagnetic environment when the flip-chip device is working.

5. The method according to claim 1, wherein The step 3 comprises: An on-wafer test bench and on-wafer probe are used to test the current-voltage curve; the multi-bias small signal scattering parameter characteristics are measured, and the voltage bias is consistent with the IV curve scanning bias point; the source and drain loads are pulled, and the operating frequency and input power of the saturated working state are set respectively, and the maximum output power and maximum power added efficiency of the device are pulled respectively, and the RF characteristics of the flip-chip microwave device are scanned, including the equal power and equal efficiency circle diagrams and harmonic distortion characteristics.

6. The method according to claim 1, wherein The step 4 comprises: Electromagnetic simulation software is used to design the de-embedding structure, and electromagnetic simulation is performed on the open and short-circuit de-embedding structures; the open and short-circuit de-embedding structures also include bumps and covers, simulating the open and short-circuit RF characteristics used in a flip-chip integration environment.

7. The method according to claim 1, characterized in that The step 4 comprises: The S parameters measured by the DUT are converted into Y parameters, and the open and short circuit de-embedding structures are established in the electromagnetic simulation software. The electromagnetic simulation simulates the S parameter characteristics of the open and short circuit structures to obtain the open circuit structure S parameters and the short circuit structure S parameters, which are converted into Y parameters respectively. The Y parameters include the open circuit admittance parameter and the short circuit admittance parameter. First, the capacitance effect of the probe pad is removed, that is, the open circuit admittance parameter after removing Yopen is equal to the admittance parameter of the DUT minus Yopen, Ym_open = Ym-Yopen, and the calculated result Ym_open is converted into an impedance parameter, that is, a Z parameter. Among them, Yopen and Yshort are the open circuit admittance parameter and the short circuit admittance parameter respectively; Ym_open is the open circuit admittance parameter after removing Yopen; Ym is the admittance parameter of the DUT; and Zm_open is the impedance parameter. Secondly, the capacitance effect of the short-circuit structure is removed, that is, the admittance parameter of the short-circuit structure after removing Yopen is Yshort_open = Yshort - Yopen, and the calculated result Yshort_open is converted to a Z parameter, which is recorded as Zm_short_open. Then, the resistance and inductance effects of the DUT are deducted to obtain the impedance parameter Zd = Zm_open - Zm_short_open. Finally, Zd is converted to an S parameter, that is, the S parameter test result after the DUT is de-embedded is obtained.

8. The method according to claim 7, characterized in that In order to utilize the RF S-parameter characteristics of the open and short circuit de-embedded structures, the optimal source impedance of the flip-chip microwave device after de-embedding is obtained, so as to realize the influence of the de-embedded test pads and connecting wires and obtain the performance of the flip-chip microwave device itself.

9. The method according to claim 1, characterized in that The step 5 comprises: According to the test data and the topology of the equivalent circuit model, the parameter values ​​of each component in the flip-chip microwave device model are determined using the model parameter extraction method; The established flip-chip microwave device model is simulated and verified, and the fitting accuracy of the test and simulation results is compared to complete the model simulation verification; the performance includes DC IV curve, small signal S parameters, noise parameters, large signal output power and intermodulation characteristics.

10. The method according to claim 9, characterized in that The topological structure of the equivalent circuit model includes three ports: a gate G, a drain D, and a source S, as well as an external parasitic parameter network and an internal intrinsic parameter network. The parasitic parameter network describes the parasitic coupling effect between the device and the substrate, the flip-chip air cavity, or the dielectric cavity, and is composed of lumped parameter and distributed parameter networks. The lumped parameters include parasitic capacitance elements Cp1, Cp2, and Cp12, parasitic resistance elements R1, R2, and R3, and the distributed parameter network includes transmission lines line1, line2, and line3. The intrinsic parameters include gate junction capacitance C1, C2, and drain-source capacitance C3, gate diodes D1 and D2, and a channel nonlinear current source I1. The gate G is connected to the transmission line line1, the gate junction capacitor C2, the transmission line line2, the parasitic resistance element R2 and the drain D in sequence through the parasitic resistance element R1; the source S is connected to the transmission line line3 through the parasitic resistance element R3; the gate diode D1 is connected in parallel with the gate junction capacitor C1, one end of the gate junction capacitor C1 is connected to the transmission line line3, and the other end is connected to one end of the gate junction capacitor C2; the channel nonlinear current source I1 is connected in parallel with the gate junction capacitor C3, one end of the gate junction capacitor C3 is connected to the transmission line line3, and the other end is connected to the gate junction capacitor C2 the other end of the gate is connected; the gate diode D2 is connected in parallel with the gate junction capacitance C2; ​​the parasitic capacitance element Cp1, the parasitic capacitance element Cp2 and the parasitic capacitance element Cp12 are connected in sequence; the common end of the parasitic capacitance element Cp1 and the parasitic capacitance element Cp2 is the same as the common end of the gate G and the parasitic resistance element R1; the common end of the parasitic capacitance element Cp1 and the parasitic capacitance element Cp2 is the same as the common end of the gate S and the parasitic resistance element R3; the common end of the parasitic capacitance element Cp2 and the parasitic capacitance element Cp12 is the same as the common end of the gate D and the parasitic resistance element R2.

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