Semiconductor device and preparation method thereof, memory and memory system

Abstract

The invention provides a semiconductor device and a preparation method thereof, a memory and a storage system.The semiconductor device comprises a ferroelectric layer group, the ferroelectric layer group comprises at least one ferroelectric layer and at least one anti-ferroelectric layer which are arranged in an overlapped mode in the first direction, and by means of the ferroelectric layer and the anti-ferroelectric layer which are arranged in an overlapped mode, the coercive field of the ferroelectric layer group is reduced; and the fatigue resistance of the semiconductor device is improved, so that the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor device and a manufacturing method thereof, a memory, and a storage system. Background Art

[0002] Ferroelectric materials are widely used in semiconductor devices. For example, ferroelectric materials can be used as capacitors in dynamic random access memory (DRAM), or ferroelectric materials can also be used in ferroelectric random access memory (FeRAM). As ferroelectric materials are widely used in semiconductor devices, the device performance of semiconductor devices using ferroelectric materials still needs to be improved.

[0003] Therefore, there is an urgent need for a semiconductor device and a manufacturing method thereof, a memory, and a storage system to solve the above technical problems. Summary of the invention

[0004] In view of this, the present application provides a semiconductor device and a preparation method thereof, a memory, and a storage system capable of improving the fatigue resistance of ferroelectric materials when applied to semiconductor devices.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a semiconductor device, comprising:

[0007] The ferroelectric layer group includes at least one ferroelectric layer and at least one antiferroelectric layer which are overlapped along a first direction.

[0008] In some embodiments of the present application, the semiconductor device also includes a first electrode and a second electrode, the first electrode and the second electrode are respectively located on opposite sides of the ferroelectric layer group along the first direction, and the extension direction of the first electrode and the second electrode is perpendicular to the first direction.

[0009] In some embodiments of the present application, the semiconductor device includes a first stacked structure, wherein the first stacked structure includes first electrodes and first insulating layers alternately stacked along a second direction;

[0010] The semiconductor device further comprises a second electrode, wherein the second electrode and the ferroelectric layer group are extended along the second direction and arranged in the first stacked structure, and the ferroelectric layer group is located between the first electrode and the second electrode along the first direction;

[0011] An extending direction of the first electrode is perpendicular to the second direction, and an extending direction of the second electrode is parallel to the second direction.

[0012] In some embodiments of the present application, along the extension direction of the first electrode, a plurality of the first electrodes and one second electrode are respectively located on two opposite sides of one ferroelectric layer group.

[0013] In some embodiments of the present application, along the extension direction of the first electrode, at least one of the antiferroelectric layers is located on a side of at least one of the ferroelectric layers close to the second electrode.

[0014] In some embodiments of the present application, the semiconductor device also includes a gate and a channel layer. Along the first direction, the gate and the channel layer are respectively located on opposite sides of the ferroelectric layer group, and the extension direction of the gate and the channel layer is perpendicular to the stacking direction of the ferroelectric layer group.

[0015] In some embodiments of the present application, the semiconductor device includes a second stacked structure, wherein the second stacked structure includes gates and second insulating layers alternately stacked along a second direction;

[0016] The semiconductor device further comprises a channel layer, wherein the channel layer and the ferroelectric layer group are extended along the second direction and arranged in the second stacked structure, and along the direction from the gate to the channel layer, the ferroelectric layer group is located between the gate and the channel layer;

[0017] An extension direction of the gate is perpendicular to the second direction, and an extension direction of the channel layer is parallel to the second direction.

[0018] In some embodiments of the present application, along the extension direction of the gate, a plurality of the gates and one channel layer are respectively located on two opposite sides of one ferroelectric layer group.

[0019] In some embodiments of the present application, along the direction from the gate to the channel layer, at least one of the antiferroelectric layers is located on a side of at least one of the ferroelectric layers close to the channel layer.

[0020] In some embodiments of the present application, at least one of the ferroelectric layers is composed of a ferroelectric material; or,

[0021] At least one of the antiferroelectric layers is composed of an antiferroelectric material.

[0022] In some embodiments of the present application, the ferroelectric layer is in direct contact with the antiferroelectric layer; or,

[0023] The ferroelectric layer group further includes at least one dielectric layer, and the dielectric layer is spaced between the adjacent ferroelectric layer and the antiferroelectric layer;

[0024] The material of the dielectric layer is different from that of the ferroelectric layer, and the material of the dielectric layer is different from that of the antiferroelectric layer.

[0025] The present application also provides a method for preparing a semiconductor device, comprising:

[0026] At least one ferroelectric layer and at least one antiferroelectric layer are overlapped along a first direction to form a ferroelectric layer group.

[0027] In some embodiments of the present application, the step of overlapping at least one ferroelectric layer and at least one antiferroelectric layer to form a ferroelectric layer group includes:

[0028] forming a first electrode;

[0029] Along the first direction, on one side of the first electrode, the ferroelectric layer and the antiferroelectric layer are overlapped to form a ferroelectric layer group;

[0030] forming a second electrode along the first direction on a side of the ferroelectric layer group away from the first electrode;

[0031] Wherein, the extending directions of the first electrode and the second electrode are perpendicular to the first direction.

[0032] In some embodiments of the present application, the step of overlapping at least one ferroelectric layer and at least one antiferroelectric layer to form a ferroelectric layer group includes:

[0033] Multiple layers of first sacrificial layers and first insulating material layers are overlapped along a second direction to form a first stacked layer;

[0034] forming a first through hole penetrating the first stacked layer along the second direction;

[0035] Alternatingly filling ferroelectric layer materials and antiferroelectric layer materials in the first through hole along the first direction to form the ferroelectric layer group;

[0036] Filling the first through hole with a second electrode material to form a second electrode;

[0037] Each of the first sacrificial layers is replaced with a first electrode.

[0038] In some embodiments of the present application, the step of overlapping at least one ferroelectric layer and at least one antiferroelectric layer to form a ferroelectric layer group includes:

[0039] forming a channel material layer;

[0040] Along the first direction, on one side of the channel material layer, the ferroelectric layer and the antiferroelectric layer are overlapped to form a ferroelectric layer group;

[0041] forming a gate along the first direction on a side of the ferroelectric layer group away from the channel material layer;

[0042] Wherein, the extending direction of the channel material layer and the gate is perpendicular to the first direction.

[0043] In some embodiments of the present application, the step of overlapping at least one ferroelectric layer and at least one antiferroelectric layer to form a ferroelectric layer group includes:

[0044] Multiple layers of second sacrificial layers and second insulating material layers are overlapped along a second direction to form a second stacked layer;

[0045] forming a second through hole penetrating the second stacked layer along the second direction;

[0046] Alternatingly filling ferroelectric layer materials and antiferroelectric layer materials in the second through hole along the first direction to form the ferroelectric layer group;

[0047] Filling the second through hole with a channel material to form a channel layer;

[0048] Each of the second sacrificial layers is replaced with a gate.

[0049] In some embodiments of the present application, the step of overlapping at least one ferroelectric layer and at least one antiferroelectric layer to form a ferroelectric layer group includes:

[0050] forming a dielectric layer between at least one of the ferroelectric layers and at least one of the antiferroelectric layers;

[0051] The material of the dielectric layer is different from that of the ferroelectric layer, and the material of the dielectric layer is different from that of the antiferroelectric layer.

[0052] In some embodiments of the present application, at least one of the ferroelectric layers is composed of a ferroelectric material; or,

[0053] At least one of the antiferroelectric layers is composed of an antiferroelectric material.

[0054] The present application also provides a memory, which includes any of the semiconductor devices described above.

[0055] The present application also provides a storage system, the storage system comprising a memory and a controller, the controller being coupled to the memory and configured to control the memory to store data;

[0056] Wherein, the memory includes any of the semiconductor devices described above.

[0057] The semiconductor device and its preparation method, memory, and storage system provided in the present application reduce the coercive electric field of the ferroelectric layer group and improve the fatigue resistance of the semiconductor device by using overlapping ferroelectric layers and antiferroelectric layers, thereby improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 is a schematic structural diagram of a semiconductor device in some embodiments;

[0060] Figure 2 It is a schematic diagram of the hysteresis loop result of the semiconductor device in the prior art;

[0061] Figure 3 This is a schematic diagram of the first structure of a semiconductor device provided in an embodiment of the present application;

[0062] Figure 4 yes Figure 3 Schematic diagram of hysteresis loop results of the semiconductor device shown;

[0063] Figure 5 is a second structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0064] Figure 6 is a third structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0065] Figure 7 is a fourth structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0066] Figure 8 is a fifth structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0067] Fig. 9 is a sixth structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0068] Fig.10 yes Fig. 9 A schematic structural diagram of the AA' section of the semiconductor device shown;

[0069] Fig.11 is a seventh structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0070] Fig.12This is an eighth structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0071] Fig.13 yes Fig.12 A schematic structural diagram of the BB' section of the semiconductor device shown;

[0072] Fig.14 is a flowchart of the steps of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0073] FIG. 15A to FIG. 15C It is a first structural schematic diagram corresponding to each process in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0074] FIG. 16A to FIG. 16E It is a second structural schematic diagram corresponding to each process in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0075] 17A to 17C It is a third structural schematic diagram corresponding to each process in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0076] 18A to 18F It is a fourth structural schematic diagram corresponding to each process in the method for preparing a semiconductor device provided in an embodiment of the present application;

[0077] Fig.19 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0078] Fig. 20 It is a schematic diagram of the structure of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0080] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0081] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0082] See also Figure 1 and Figure 2 In some embodiments of the semiconductor device 100', the use of the ferroelectric layer 101' alone results in a larger value of the coercive electric field |Ec1| of the semiconductor device 100', and a weaker fatigue resistance of the semiconductor device 100', which makes it difficult to improve the reliability of the semiconductor device 100'.

[0083] See also Figures 3 to 13 In an embodiment of the present application, a semiconductor device is provided, comprising:

[0084] The ferroelectric layer group 110 includes at least one ferroelectric layer 101 and at least one antiferroelectric layer 102 which are overlapped and arranged along a first direction Y1.

[0085] See also Figures 3 to 8 In some embodiments of the present application, a semiconductor device 100 further includes a first electrode 120 and a second electrode 130, wherein the first electrode 120 and the second electrode 130 are respectively located on opposite sides of the ferroelectric layer group 110 in the first direction Y1, and the extension direction of the first electrode 120 and the second electrode 130 is perpendicular to the first direction Y1. It can be understood that the vertical in the present application refers to the vertical within a certain angle error range, for example, 85° to 95° can be interpreted as vertical.

[0086] See also Figures 3 to 8In some embodiments of the present application, the first electrode 120, the second electrode 130 and the ferroelectric layer group 110 can constitute a capacitor. By applying an electric field directed from the first electrode 120 to the second electrode 130, the ferroelectric layer 101 and the antiferroelectric layer 102 in the ferroelectric layer group 110 can be in a first polarization state, that is, data "1" or "0" is written to the ferroelectric layer group 110; by applying an electric field directed from the second electrode 130 to the first electrode 120, the ferroelectric layer 101 and the antiferroelectric layer 102 in the ferroelectric layer group 110 can be in a second polarization state different from the first polarization state, that is, data "0" or "1" is written to the ferroelectric layer group 110, which is different from the data written when the ferroelectric layer 101 is in the first polarization state. Please refer to Figure 3 By overlapping the antiferroelectric layer 102 and the ferroelectric layer 101, the coercive electric field |Ec2| (such as Figure 4 As shown in the figure, the value |Ec1| is reduced and is smaller than |Ec1|, thereby improving the fatigue resistance of the semiconductor device 100 and enhancing the reliability of the semiconductor device 100.

[0087] In some embodiments of the present application, when the first electrode 120, the second electrode 130 and the ferroelectric layer group 110 form a capacitor, the semiconductor device 100 further includes a transistor (not shown), which is coupled to the capacitor. When the extension direction of the first electrode 120 and the second electrode 130 is perpendicular to the first direction Y1, the transistor is located on a side of the first electrode 120 away from the second electrode 130 along the first direction Y1, and the drain of the transistor or the source of the transistor is coupled to the first electrode 120; or, the transistor is located on a side of the second electrode 130 away from the first electrode 120 along the first direction Y1, and the drain of the transistor or the source of the transistor is coupled to the second electrode 130.

[0088] In some embodiments of the present application, the material of the first electrode 120 and the material of the second electrode 130 may be the same or different, and the material of the first electrode 120 and the material of the second electrode 130 may be respectively selected from at least one of conductive materials such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium.

[0089] See also Fig. 9 and Fig.10In some embodiments of the present application, another semiconductor device 200 includes a first stacking structure 140, wherein the first stacking structure 140 includes first electrodes 120 and first insulating layers 141 alternately stacked along a second direction Y2. The semiconductor device 200 also includes a second electrode 130, wherein the second electrode 130 and the ferroelectric layer group 110 are extended along the second direction Y2 in the first stacking structure 140, and the ferroelectric layer group 110 is located between the first electrode 120 and the second electrode 130 along the first direction Y1. The extension direction of the first electrode 120 is perpendicular to the second direction Y2, and the extension direction of the second electrode 130 is parallel to the second direction Y2.

[0090] See also Fig. 9 and Fig.10 In some embodiments of the present application, along the extension direction of the first electrode 120 , a plurality of the first electrodes 120 and one second electrode 130 are respectively located on two opposite sides of one ferroelectric layer group 110 .

[0091] See also Fig. 9 In some embodiments of the present application, one first electrode 120 and one second electrode 130, and the ferroelectric layer group 110 located between the first electrode 120 and the second electrode 130 in the first direction Y1 together constitute a capacitor. In the second direction Y2, a plurality of overlapping first electrodes 120, the second electrode 130 extending along the second direction Y2 and arranged in the first stacked structure 140, and the ferroelectric layer group 110 extending along the second direction Y2 and arranged in the first stacked structure 140 and located between the first electrode 120 and the second electrode 130 in the first direction Y1, can together constitute a plurality of capacitors arranged in parallel along the second direction Y2, thereby forming the semiconductor device 200 with a three-dimensional structure.

[0092] In some embodiments of this application, please refer to Fig. 9 and Fig.10, along the extension direction of the first electrode 120, at least one of the antiferroelectric layers 102 is located on the side of at least one of the ferroelectric layers 101 close to the second electrode 130; or, along the extension direction of the first electrode 120, at least one of the ferroelectric layers 101 is located on the side of at least one of the antiferroelectric layers 102 close to the second electrode 130 (not shown). When the first electrode 120 and the first insulating layer 141 are alternately stacked along the second direction Y2, and the second electrode 130 and the ferroelectric layer group 110 are extended along the second direction Y2 in the first stacked structure 140, the first electrode 120 is connected to the common end, and the direction of the electric field between the first electrode 120 and the second electrode 130 is changed by adjusting the voltage carried by the second electrode 130, so as to write data "0" or "1" to the ferroelectric layer group 110. Therefore, in the extension direction of the first electrode 120, according to Gauss's theorem, the closer the position is to the second electrode 130, the greater the electric field strength is. The antiferroelectric layer 102 is made of antiferroelectric material, and the ferroelectric layer 101 is made of ferroelectric material. The antiferroelectric material has a stronger ability to carry an electric field. Therefore, preferably, along the extension direction of the first electrode 120, at least one of the antiferroelectric layers 102 is located on the side of at least one of the ferroelectric layers 101 close to the second electrode 130. For example, when the ferroelectric layer group 110 is composed of one ferroelectric layer 101 and one antiferroelectric layer 102, in the extension direction of the first electrode 120, the antiferroelectric layer 102 is located between the ferroelectric layer 101 and the second electrode 130.

[0093] See also Fig.11 In some embodiments of the present application, the ferroelectric layer group 110 can be used for a ferroelectric field effect transistor. Fig.11 The semiconductor device 300 as a ferroelectric field effect transistor further includes a gate 150 and a channel layer 161. The gate 150 and the channel layer 161 are respectively located at opposite sides of the ferroelectric layer group 110 along the first direction Y1, and the extension direction of the gate 150 and the channel layer 161 is perpendicular to the stacking direction of the ferroelectric layer group 110. That is, along the first direction Y1, the ferroelectric layer group 110 is between the gate 150 and the channel layer 161.

[0094] In some embodiments of the present application, in the first direction Y1, the side of the ferroelectric layer group 110 close to the channel layer 161 is in direct contact with the channel layer 161 (not shown); or, refer to Fig.11 The semiconductor device 300 includes an interface layer 181 located between the ferroelectric layer group 110 and the channel layer 161 in the first direction Y1, and the material of the interface layer 181 can be selected from at least one of silicon oxide and silicon nitride.

[0095] In some embodiments of the present application, the semiconductor device 300 further includes a source and a drain located on opposite sides of the channel layer 161 in a third direction Y3 , and the third direction Y3 intersects with the first direction Y1 .

[0096] In some embodiments of the present application, the third direction Y3 may be perpendicular to the first direction Y1 , and the third direction Y3 is parallel to an extension direction of the gate 150 .

[0097] In some embodiments of the present application, the material of the channel layer 161 may include, but is not limited to, amorphous silicon, polycrystalline silicon, or single crystal silicon, or any suitable semiconductor material. The channel layer 161, the source electrode, and the drain electrode may be formed by doping or implanting a channel material layer. The material of the channel material layer includes, but is not limited to, amorphous silicon, polycrystalline silicon, or single crystal silicon, or any suitable semiconductor material. The two opposite sides of the channel material layer in the third direction Y3 are doped or implanted respectively, thereby forming a heavily doped portion 162 and a lightly doped portion 163 (such as a lightly doped portion 163) located between the heavily doped portions 162. Fig.11 As shown in the figure, the heavily doped portions 162 located on opposite sides of the channel material layer in the third direction Y3 respectively form the source and the drain. The doped or injected elements may include group III elements such as B, Al, Ga, In, or group V elements such as P, As, Sb, etc. The undoped region in the channel material layer forms the channel layer 161, and the channel layer 161 is located between the two lightly doped portions 163 in the third direction Y3.

[0098] In some embodiments of the present application, the material of the gate 150 may include at least one of conductive materials such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium.

[0099] See also Fig.12 and 13 In some embodiments of the present application, another semiconductor device 400 includes a second stacked structure 190, and the second stacked structure 190 includes a gate 150 and a second insulating layer 191 alternately stacked along a second direction Y2. The semiconductor device 400 also includes a channel layer 161, and the channel layer 161 and the ferroelectric layer group 110 are extended along the second direction Y2 in the second stacked structure 190, and along the direction from the gate 150 to the channel layer 161, the ferroelectric layer group 110 is located between the gate 150 and the channel layer 161. The extension direction of the gate 150 is perpendicular to the second direction Y2, and the extension direction of the channel layer 161 is parallel to the second direction Y2.

[0100] See also Fig.12 and Fig.13 In some embodiments of the present application, along the extension direction of the gate 150, a plurality of the gates 150 and a channel layer 161 are respectively located on opposite sides of a ferroelectric layer group 110. The plurality of gates 150 are alternately arranged along the second direction Y2, so that a plurality of memory cells are stacked along the second direction Y2, thereby obtaining the semiconductor device 400 with a three-dimensional structure. The change of the voltage on the gate 150 changes the polarization state of the ferroelectric layer 101 in the ferroelectric layer group 110, thereby changing the resistance of the channel layer 161, achieving conduction and cutoff, thereby accessing data.

[0101] In some embodiments of the present application, the semiconductor device 400 further includes a source and a drain ( Fig.12 and Fig.13 (not shown), along the second direction Y2, the source and the drain are respectively located at two ends of the channel layer 161.

[0102] See also Fig.12 and Fig.13 In some embodiments of the present application, the semiconductor device 400 further includes a filling layer 182 extending along the second direction Y2 and disposed in the second stacked structure 190. The filling layer 182 plays a mechanical support role, and the material of the filling layer 182 can be selected from at least one of silicon oxide and silicon nitride. Along the direction from the gate 150 to the channel layer 161, the filling layer 182 is located on a side of the channel layer 161 away from the ferroelectric layer group 110.

[0103] See also Fig.12 and Fig.13 In some embodiments of the present application, the semiconductor device 400 includes an interface layer 181 located between the ferroelectric layer group 110 and the channel layer 161 in the direction from the gate 150 to the channel layer 161, and the material of the interface layer 181 can be selected from at least one of silicon oxide and silicon nitride.

[0104] In some embodiments of the present application, Fig.12 and Fig.13 As shown, along the direction from the gate 150 to the channel layer 161, at least one of the antiferroelectric layers 102 is located on a side of at least one of the ferroelectric layers 101 close to the channel layer 161; or, along the direction from the gate 150 to the channel layer 161, at least one of the ferroelectric layers 101 is located on a side of at least one of the antiferroelectric layers 102 close to the channel layer 161 (not shown).

[0105] In some embodiments of the present application, at least one of the ferroelectric layers 101 is composed of a ferroelectric material. Alternatively, at least one of the antiferroelectric layers 102 is composed of an antiferroelectric material.

[0106] In some embodiments of the present application, the ferroelectric material may be selected from the following compounds in orthorhombic phase: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Sia(HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped dioxide (Zr a (HfO2) b ), wherein a and b are both selected from positive numbers. The antiferroelectric material may be selected from the following tetragonal compounds: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Sia(HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ), zirconium oxide (ZrO), wherein a and b are both selected from positive numbers.

[0107] In some embodiments of the present application, any of the ferroelectric layers 101 may be composed of ferroelectric materials. Alternatively, any of the antiferroelectric layers 102 may be composed of antiferroelectric materials. By overlapping the antiferroelectric layer 102 and the ferroelectric layer 101, the coercive electric field of the ferroelectric layer group 110 is reduced, and the fatigue resistance of the semiconductor device is improved. At the same time, by separately arranging the ferroelectric layer 101 and the antiferroelectric layer 102, the material composition of the ferroelectric layer 101 and the antiferroelectric layer 102 is made single, which improves the stability of the ferroelectric layer 101 and the antiferroelectric layer 102 and enhances the reliability of the semiconductor device.

[0108] In some embodiments of the present application, at least one of the ferroelectric layers 101 may be composed of a single-component ferroelectric material. Alternatively, at least one of the antiferroelectric layers 102 may be composed of a single-component antiferroelectric material.

[0109] In some embodiments of the present application, any of the ferroelectric layers 101 may be composed of a single-component ferroelectric material. Alternatively, any of the antiferroelectric layers 102 may be composed of a single-component antiferroelectric material. By making the materials constituting the ferroelectric layer 101 and the antiferroelectric layer 102 single-component, it is helpful to avoid the instability of properties caused by the mixing of different ferroelectric materials or the mixing of different antiferroelectric materials, and further improve the reliability of the semiconductor device.

[0110] In some embodiments of the present application, in the ferroelectric layer group 110, the number of the ferroelectric layers 101 may be N (N is an integer greater than or equal to 1), and the number of the antiferroelectric layers 102 may be the same as the number of the ferroelectric layers 101 (eg Figure 3 , Figure 7 As shown), the number of the antiferroelectric layers 102 is also N; the number of the antiferroelectric layers 102 may be greater than the number of the ferroelectric layers 101 (as shown Figure 5 As shown), the number of the antiferroelectric layers 102 is (N+1); the number of the antiferroelectric layers 102 may be less than the number of the ferroelectric layers 101 (as shown Figure 6 As shown), the number of the ferroelectric layers 101 may be M (M is an integer greater than or equal to 2), and the number of the antiferroelectric layers 102 is (M-1).

[0111] In some embodiments of the present application, in consideration of the improvement of fatigue resistance and process level of the ferroelectric layer group 110, the number of the antiferroelectric layers 102 may be 1 or 2, and the number of the ferroelectric layers 101 may be 1 or 2. For example, the number of the ferroelectric layer 101 may be 1, and the number of the antiferroelectric layer 102 may be 1 (e.g., Figure 3 The number of the ferroelectric layers 101 may be 2, the number of the antiferroelectric layer 102 may be 1, and the antiferroelectric layer 102 is located between the two ferroelectric layers 101 in the first direction Y1 (as shown in FIG. 1 ); Figure 6 The number of the ferroelectric layer 101 may be 1, the number of the antiferroelectric layer 102 may be 2, and the ferroelectric layer 101 is located between the two antiferroelectric layers 102 in the first direction Y1 (as shown in FIG. 1 ); Figure 5 The number of the ferroelectric layers 101 may be 2, the number of the antiferroelectric layers 102 may be 2, and the ferroelectric layers 101 and the antiferroelectric layers 102 are arranged to overlap in the first direction Y1 (as shown in FIG. 1 ); Figure 7 shown).

[0112] See also Figures 3 to 7 In some embodiments of the present application, the ferroelectric layer 101 is in direct contact with the antiferroelectric layer 102 .

[0113] In some embodiments of the present application, the ferroelectric layer group 110 further includes at least one dielectric layer 103 (eg Figure 8As shown in the figure, the dielectric layer 103 is spaced between the adjacent ferroelectric layer 101 and the antiferroelectric layer 102. The material of the dielectric layer 103 is different from that of the ferroelectric layer 101, and the material of the dielectric layer 103 is different from that of the antiferroelectric layer 102. The arrangement of the dielectric layer 103 is conducive to blocking the current leakage channel generated by oxygen vacancies or grain boundaries between the adjacent ferroelectric layer 101 and the antiferroelectric layer 102, further improving the reliability of the semiconductor device.

[0114] In some embodiments of the present application, the material of the dielectric layer 103 is selected from at least one of aluminum oxide, silicon dioxide, nitrogen-doped silicon dioxide, and aluminum-doped silicon dioxide.

[0115] In some embodiments of the present application, the thickness of the dielectric layer 103 is as thin as possible while taking into account the ability to block current leakage channels formed by oxygen vacancies or grain boundaries and the process level. For example, the thickness of the dielectric layer 103 may be about 1 nanometer, for example, it may be 0.95 nanometers, 0.98 nanometers, 1 nanometer, 1.02 nanometers, etc.

[0116] In some embodiments of the present application, the number of the dielectric layers 103 in the ferroelectric layer group 110 is an integer greater than or equal to 1. Preferably, the number of the dielectric layers 103 may be 1 or 2 while taking into account both the blocking effect of the current leakage channel and the process level.

[0117] The semiconductor device provided in the present application reduces the coercive electric field of the ferroelectric layer group 110 by using the overlapping ferroelectric layer 101 and the antiferroelectric layer 102, improves the fatigue resistance of the semiconductor device, and thus enhances the reliability of the semiconductor device.

[0118] See also Fig.14 In an embodiment of the present application, a method for preparing a semiconductor device is provided, comprising:

[0119] Step S100 : at least one ferroelectric layer 101 and at least one antiferroelectric layer 102 are overlapped along a first direction Y1 to form a ferroelectric layer group 110 .

[0120] Specifically, in some embodiments of the present application, at least one ferroelectric layer 101 and at least one antiferroelectric layer 102 overlappingly arranged in the first direction Y1 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0121] In some embodiments of the present application, please refer to FIG. 15A to FIG. 15C , step S100 includes:

[0122] Step S111: forming a first electrode 120;

[0123] Step S112: along the first direction Y1, on one side of the first electrode 120, the ferroelectric layer 101 and the antiferroelectric layer 102 are overlapped to form a ferroelectric layer group 110; and,

[0124] Step S113 : forming a second electrode 130 along the first direction Y1 on a side of the ferroelectric layer group 110 away from the first electrode 120 .

[0125] The extending direction of the first electrode 120 formed in step S111 is perpendicular to the first direction Y1, and the extending direction of the second electrode 130 formed in step S113 is perpendicular to the first direction Y1. It can be understood that the vertical in the present application refers to the vertical within a certain angle error range, for example, 85° to 95° can be interpreted as vertical.

[0126] In some embodiments of the present application, the material of the first electrode 120 and the material of the second electrode 130 may be the same or different, and the material of the first electrode 120 and the material of the second electrode 130 may be respectively selected from at least one of conductive materials such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium or ruthenium.

[0127] In some embodiments of the present application, please refer to FIG. 16A to FIG. 16E , step S100 includes:

[0128] Step S121: multiple layers of first sacrificial layers 142 and first insulating material layers 143 are overlapped along the second direction Y2 to form a first stacked layer 144;

[0129] Step S122: forming a first through hole H1 penetrating the first stacked layer 144 along the second direction Y2;

[0130] Step S123: Fig. 16B The first through hole H1 is filled with ferroelectric layer materials and antiferroelectric layer materials alternately along the first direction Y1 to form the ferroelectric layer group 110;

[0131] In some embodiments of the present application, the ferroelectric layer group 110 extends along the second direction Y2 and is disposed as follows: Fig. 16B As shown in the first through hole H1.

[0132] Step S124: Fig. 16B The first through hole H1 is filled with a second electrode material to form a second electrode 130;

[0133] In some embodiments of the present application, the second electrode 130 extends along the second direction Y2 and is disposed as follows: Fig. 16B As shown in the first through hole H1.

[0134] Step S125 : replacing each of the first sacrificial layers with the first electrodes 120 .

[0135] In some embodiments of the present application, step S125 further includes: the first insulating material layer 143 forms a first insulating layer 141 .

[0136] See also Fig.16E In some embodiments of the present application, along the extension direction of the first electrode 120 , a plurality of the first electrodes 120 and one second electrode 130 are respectively located on two opposite sides of one ferroelectric layer group 110 .

[0137] See also Fig.16E In some embodiments of the present application, one first electrode 120 and one second electrode 130, and the ferroelectric layer group 110 located between the first electrode 120 and the second electrode 130 in the first direction Y1 together constitute a capacitor. In the second direction Y2, a plurality of overlapping first electrodes 120, the second electrode 130 extending along the second direction Y2 and arranged in the first stacking structure 140, and the ferroelectric layer group 110 extending along the second direction Y2 and arranged in the first stacking structure 140 and located between the first electrode 120 and the second electrode 130 in the first direction Y1, can together constitute a plurality of capacitors arranged in parallel along the second direction Y2, thereby forming the semiconductor device with a three-dimensional structure.

[0138] In some embodiments of the present application, please refer to 17A to 17C , step S100 includes:

[0139] Step S131: forming a channel material layer 164;

[0140] Step S132: along the first direction Y1, on one side of the channel material layer 164, the ferroelectric layer 101 and the antiferroelectric layer 102 are overlapped to form a ferroelectric layer group 110; and,

[0141] Step S133 : forming a gate along the first direction Y1 on a side of the ferroelectric layer group 110 away from the channel material layer 164 .

[0142] In some embodiments of the present application, in step S131 , the extension direction of the channel material layer 164 formed is perpendicular to the first direction Y1 , and in step S133 , the extension direction of the gate 150 formed is perpendicular to the first direction Y1 .

[0143] In some embodiments of the present application, in step S131 , the extension direction of the channel material layer 164 formed is perpendicular to the first direction Y1 , and in step S133 , the extension direction of the gate 150 formed is perpendicular to the first direction Y1 .

[0144] In some embodiments of the present application, after step S133, the method further includes:

[0145] In step S134 , the channel material layer 164 is partially conductively processed to form a channel layer 161 and heavily doped portions 162 located at two opposite sides of the channel layer 161 in the third direction Y3 .

[0146] In some embodiments of the present application, the heavily doped portions 162 located at opposite sides of the channel material layer 164 in the third direction Y3 form the source and the drain, respectively.

[0147] Wherein, the third direction Y3 intersects with the first direction Y1.

[0148] In some embodiments of the present application, the third direction Y3 may be perpendicular to the first direction Y1 , and the third direction Y3 is parallel to an extension direction of the gate 150 .

[0149] In some embodiments of the present application, in step S134 , it further includes: forming a lightly doped portion 163 between the heavily doped portions 162 in the third direction Y3 .

[0150] In some embodiments of the present application, the channel layer 161 is located between the two lightly doped portions 163 in the third direction Y3 .

[0151] In some embodiments of the present application, after step S131 and before step S132, the following further includes:

[0152] Step S135 : forming an interface layer 181 along the first direction Y1 on a side of the channel material layer 164 close to a preset position of the ferroelectric layer group 110 .

[0153] In some embodiments of the present application, the material of the interface layer 181 may be selected from at least one of silicon oxide and silicon nitride.

[0154] In some embodiments of the present application, please refer to 18A to 18F, step S100 includes:

[0155] Step S141: multiple layers of second sacrificial layers 192 and second insulating material layers 193 are overlapped along the second direction Y2 to form a second stacked layer 194;

[0156] Step S142: forming a second through hole H2 penetrating the second stack layer 194 along the second direction Y2;

[0157] Step S143: Fig.18B The second through hole H2 is filled with ferroelectric layer materials and antiferroelectric layer materials alternately along the first direction Y1 to form the ferroelectric layer group 110;

[0158] In some embodiments of the present application, the ferroelectric layer group 110 extends along the second direction Y2 and is disposed as follows: Fig.18B The second through hole H2 is shown.

[0159] Step S144: Fig.18B The second through hole H2 is filled with a channel material to form a channel layer 161;

[0160] In some embodiments of the present application, the channel layer 161 extends along the second direction Y2 and is disposed at Fig.18B The second through hole H2 is shown.

[0161] Step S145 : replacing each of the second sacrificial layers 192 with a gate 150 .

[0162] In some embodiments of the present application, step S145 further includes: the second insulating material layer 193 forms a second insulating layer 191 .

[0163] In some embodiments of the present application, after step S143 and before step S144, the following further includes:

[0164] Step S146: Fig.18B The second through hole H2 is filled with an interface layer material to form an interface layer 181 .

[0165] In some embodiments, the material of the interface layer 181 may be selected from at least one of silicon oxide and silicon nitride.

[0166] In some embodiments of the present application, after step S144 and before step S145, the following is further included:

[0167] Step S147: Fig.18B As shown, the second through hole H2 is filled with a filling layer material to form a filling layer 182 .

[0168] In some embodiments, the material of the filling layer 182 can be selected from at least one of silicon oxide and silicon nitride.

[0169] In some embodiments of the present application, the semiconductor device further includes a source and a drain ( Fig.18F (not shown), the source may be formed before step S141, and the drain may be formed after step S145.

[0170] In some embodiments of the present application, step S100 further includes:

[0171] Step S151: forming a layer between at least one of the ferroelectric layers 101 and at least one of the antiferroelectric layers 102 as shown in FIG. Figure 8 The dielectric layer 103 is shown.

[0172] The material of the dielectric layer 103 is different from that of the ferroelectric layer 101 , and the material of the dielectric layer 103 is different from that of the antiferroelectric layer 102 .

[0173] In some embodiments of the present application, step S151 is performed in step S112, step S123, step S132 or step S143.

[0174] The provision of the dielectric layer 103 is beneficial to blocking the current leakage channel between the adjacent ferroelectric layer 101 and the antiferroelectric layer 102 due to oxygen vacancies or grain boundaries, further improving the reliability of the semiconductor device.

[0175] In some embodiments of the present application, the material of the dielectric layer 103 is selected from at least one of aluminum oxide, silicon dioxide, nitrogen-doped silicon dioxide, and aluminum-doped silicon dioxide.

[0176] In some embodiments of the present application, the thickness of the dielectric layer 103 is as thin as possible while taking into account the ability to block current leakage channels formed by oxygen vacancies or grain boundaries and the process level. For example, the thickness of the dielectric layer 103 may be about 1 nanometer, for example, it may be 0.95 nanometers, 0.98 nanometers, 1 nanometer, 1.02 nanometers, etc.

[0177] In some embodiments of the present application, the number of the dielectric layers 103 in the ferroelectric layer group 110 is an integer greater than or equal to 1. Preferably, the number of the dielectric layers 103 may be 1 or 2 while taking into account both the blocking effect of the current leakage channel and the process level.

[0178] In some embodiments of the present application, at least one of the ferroelectric layers 101 is composed of a ferroelectric material. Alternatively, at least one of the antiferroelectric layers 102 is composed of an antiferroelectric material.

[0179] In some embodiments of the present application, the ferroelectric material may be selected from the following compounds in orthorhombic phase: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Sia(HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped dioxide (Zr a (HfO2) b ), wherein a and b are both selected from positive numbers. The antiferroelectric material may be selected from the following tetragonal compounds: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Sia(HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ), zirconium oxide (ZrO), wherein a and b are both selected from positive numbers.

[0180] In some embodiments of the present application, any of the ferroelectric layers 101 may be composed of ferroelectric materials. Alternatively, any of the antiferroelectric layers 102 may be composed of antiferroelectric materials. By overlapping the antiferroelectric layer 102 and the ferroelectric layer 101, the coercive electric field of the ferroelectric layer group 110 is reduced, and the fatigue resistance of the semiconductor device is improved. At the same time, by separately arranging the ferroelectric layer 101 and the antiferroelectric layer 102, the material composition of the ferroelectric layer 101 and the antiferroelectric layer 102 is made single, which improves the stability of the ferroelectric layer 101 and the antiferroelectric layer 102 and enhances the reliability of the semiconductor device.

[0181] In some embodiments of the present application, at least one of the ferroelectric layers 101 may be composed of a single-component ferroelectric material. Alternatively, at least one of the antiferroelectric layers 102 may be composed of a single-component antiferroelectric material.

[0182] In some embodiments of the present application, any of the ferroelectric layers 101 may be composed of a single-component ferroelectric material. Alternatively, any of the antiferroelectric layers 102 may be composed of a single-component antiferroelectric material. By making the materials constituting the ferroelectric layer 101 and the antiferroelectric layer 102 single-component, it is helpful to avoid the instability of properties caused by the mixing of different ferroelectric materials or the mixing of different antiferroelectric materials, and further improve the reliability of the semiconductor device.

[0183] In some embodiments of the present application, in the ferroelectric layer group 110, the number of the ferroelectric layers 101 may be N (N is an integer greater than or equal to 1), and the number of the antiferroelectric layers 102 may be the same as the number of the ferroelectric layers 101 (eg Figure 3 , Figure 7 As shown), the number of the antiferroelectric layers 102 is also N; the number of the antiferroelectric layers 102 may be greater than the number of the ferroelectric layers 101 (as shown Figure 5 As shown), the number of the antiferroelectric layers 102 is (N+1); the number of the antiferroelectric layers 102 may be less than the number of the ferroelectric layers 101 (as shown Figure 6 As shown), the number of the ferroelectric layers 101 may be M (M is an integer greater than or equal to 2), and the number of the antiferroelectric layers 102 is (M-1).

[0184] In some embodiments of the present application, taking into account the improvement of fatigue resistance and the process level of the ferroelectric layer group 110, the number of the antiferroelectric layers 102 can be 1 or 2, and the number of the ferroelectric layers 101 can be 1 or 2. For example, the number of the ferroelectric layer 101 may be 1, and the number of the antiferroelectric layer 102 may be 1; the number of the ferroelectric layer 101 may be 2, and the number of the antiferroelectric layer 102 may be 1, and the antiferroelectric layer 102 is located between two of the ferroelectric layers 101 in the first direction Y1; the number of the ferroelectric layer 101 may be 1, and the number of the antiferroelectric layer 102 may be 2, and the ferroelectric layer 101 is located between two of the antiferroelectric layers 102 in the first direction Y1; the number of the ferroelectric layer 101 may be 2, and the number of the antiferroelectric layer 102 may be 2, and the ferroelectric layer 101 and the antiferroelectric layer 102 are overlapped in the first direction Y1.

[0185] The method for preparing a semiconductor device provided in an embodiment of the present application reduces the coercive electric field of the ferroelectric layer group 110 by forming the overlapping ferroelectric layer 101 and the antiferroelectric layer 102, improves the fatigue resistance of the semiconductor device, and thus enhances the reliability of the semiconductor device.

[0186] See also Fig.19 , an embodiment of the present application further provides a memory 11, which includes the semiconductor device 100 / 200 / 300 / 400 in any of the above embodiments.

[0187] In some embodiments of the present application, the memory 11 includes a memory chip 11a and a peripheral circuit chip 11b, the peripheral circuit chip 11b is electrically connected to the memory chip 11a, and the peripheral circuit chip 11b can store data in the memory chip 11a or read data from the memory chip 11a. The memory chip 11a and / or the peripheral circuit chip 11b may include the semiconductor device 100 / 200 / 300 / 400 in any of the above embodiments.

[0188] Specifically, the memory 11 may be a three-dimensional memory (eg, a 3D NAND memory). It is understood that the memory provided by the embodiment of the present application has the same beneficial effects as the semiconductor device provided by the embodiment of the present application due to the semiconductor device provided by the embodiment of the present application.

[0189] See also Fig. 20 An embodiment of the present application further provides a storage system 10, which includes a controller 12 and a memory 11. The controller 12 is coupled to the memory 11 and is used to control the memory 11 to store data; wherein the memory 11 includes the semiconductor device 100 in any of the above embodiments.

[0190] The storage system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The controller may be configured to control operations of the semiconductor package structure, such as read, erase, and program operations.

[0191] In some embodiments of the present application, the controller 12 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0192] In some embodiments of the present application, the controller 12 is designed to operate in a solid state drive (SSD) or an embedded multi media card (eMMC), and the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0193] The present application provides a semiconductor device and a preparation method thereof, a memory, and a storage system. The semiconductor device includes a ferroelectric layer group, and the ferroelectric layer group includes at least one ferroelectric layer and at least one antiferroelectric layer overlapped along a first direction. The present application reduces the coercive electric field of the ferroelectric layer group by using overlapping ferroelectric layers and antiferroelectric layers, improves the fatigue resistance of the semiconductor device, and thus improves the reliability of the semiconductor device.

[0194] The semiconductor device and its preparation method, memory, and storage system provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, characterized in that: include: The ferroelectric layer group includes at least one ferroelectric layer and at least one antiferroelectric layer which are overlapped along a first direction.

2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a first electrode and a second electrode. The first electrode and the second electrode are respectively located at opposite sides of the ferroelectric layer group along the first direction, and the extension direction of the first electrode and the second electrode is perpendicular to the first direction.

3. The semiconductor device according to claim 1, wherein The semiconductor device comprises a first stacking structure, wherein the first stacking structure comprises first electrodes and first insulating layers alternately stacked along a second direction; The semiconductor device further comprises a second electrode, wherein the second electrode and the ferroelectric layer group are extended along the second direction and arranged in the first stacked structure, and the ferroelectric layer group is located between the first electrode and the second electrode along the first direction; An extending direction of the first electrode is perpendicular to the second direction, and an extending direction of the second electrode is parallel to the second direction.

4. The semiconductor device according to claim 3, characterized in that Along the extending direction of the first electrode, a plurality of the first electrodes and one second electrode are respectively located at two opposite sides of one ferroelectric layer group.

5. The semiconductor device according to claim 3, wherein: Along the extending direction of the first electrode, at least one of the antiferroelectric layers is located on a side of at least one of the ferroelectric layers close to the second electrode.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a gate and a channel layer. Along the first direction, the gate and the channel layer are respectively located on opposite sides of the ferroelectric layer group, and the extension direction of the gate and the channel layer is perpendicular to the stacking direction of the ferroelectric layer group.

7. The semiconductor device according to claim 1, wherein: The semiconductor device comprises a second stacked structure, wherein the second stacked structure comprises gates and second insulating layers alternately stacked along a second direction; The semiconductor device further comprises a channel layer, wherein the channel layer and the ferroelectric layer group are extended along the second direction and arranged in the second stacked structure, and along the direction from the gate to the channel layer, the ferroelectric layer group is located between the gate and the channel layer; An extension direction of the gate is perpendicular to the second direction, and an extension direction of the channel layer is parallel to the second direction.

8. The semiconductor device according to claim 7, wherein: Along the extension direction of the gate, a plurality of the gates and one channel layer are respectively located on two opposite sides of one ferroelectric layer group.

9. The semiconductor device according to claim 7, wherein: Along the direction from the gate to the channel layer, at least one of the antiferroelectric layers is located on a side of at least one of the ferroelectric layers close to the channel layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein: At least one of the ferroelectric layers is composed of a ferroelectric material; or, At least one of the antiferroelectric layers is composed of an antiferroelectric material.

11. The semiconductor device according to any one of claims 1 to 9, characterized in that The ferroelectric layer is in direct contact with the antiferroelectric layer; or, The ferroelectric layer group further includes at least one dielectric layer, and the dielectric layer is spaced between the adjacent ferroelectric layer and the antiferroelectric layer; The material of the dielectric layer is different from that of the ferroelectric layer, and the material of the dielectric layer is different from that of the antiferroelectric layer.

12. A method for preparing a semiconductor device, characterized in that: include: At least one ferroelectric layer and at least one antiferroelectric layer are overlapped along a first direction to form a ferroelectric layer group.

13. The method for preparing a semiconductor device according to claim 12, wherein: The step of overlapping the at least one ferroelectric layer and the at least one antiferroelectric layer to form a ferroelectric layer group comprises: forming a first electrode; Along the first direction, on one side of the first electrode, the ferroelectric layer and the antiferroelectric layer are overlapped to form a ferroelectric layer group; forming a second electrode along the first direction on a side of the ferroelectric layer group away from the first electrode; Wherein, the extending directions of the first electrode and the second electrode are perpendicular to the first direction.

14. The method for preparing a semiconductor device according to claim 12, wherein: The step of overlapping the at least one ferroelectric layer and the at least one antiferroelectric layer to form a ferroelectric layer group comprises: Multiple layers of first sacrificial layers and first insulating material layers are overlapped along a second direction to form a first stacked layer; forming a first through hole penetrating the first stacked layer along the second direction; Alternatingly filling ferroelectric layer materials and antiferroelectric layer materials in the first through hole along the first direction to form the ferroelectric layer group; Filling the first through hole with a second electrode material to form a second electrode; Each of the first sacrificial layers is replaced with a first electrode.

15. The method for preparing a semiconductor device according to claim 12, wherein: The step of overlapping the at least one ferroelectric layer and the at least one antiferroelectric layer to form a ferroelectric layer group comprises: forming a channel material layer; Along the first direction, on one side of the channel material layer, the ferroelectric layer and the antiferroelectric layer are overlapped to form a ferroelectric layer group; forming a gate along the first direction on a side of the ferroelectric layer group away from the channel material layer; Wherein, the extension direction of the channel material layer and the gate is perpendicular to the first direction.

16. The method for preparing a semiconductor device according to claim 12, wherein: The step of overlapping the at least one ferroelectric layer and the at least one antiferroelectric layer to form a ferroelectric layer group comprises: Multiple layers of second sacrificial layers and second insulating material layers are overlapped along a second direction to form a second stacked layer; forming a second through hole penetrating the second stacked layer along the second direction; Alternatingly filling ferroelectric layer materials and antiferroelectric layer materials in the second through hole along the first direction to form the ferroelectric layer group; Filling the second through hole with a channel material to form a channel layer; Each of the second sacrificial layers is replaced with a gate.

17. The method for preparing a semiconductor device according to any one of claims 12 to 16, characterized in that: The step of overlapping the at least one ferroelectric layer and the at least one antiferroelectric layer to form a ferroelectric layer group comprises: forming a dielectric layer between at least one of the ferroelectric layers and at least one of the antiferroelectric layers; The material of the dielectric layer is different from that of the ferroelectric layer, and the material of the dielectric layer is different from that of the antiferroelectric layer.

18. The method for preparing a semiconductor device according to any one of claims 12 to 16, characterized in that: At least one of the ferroelectric layers is composed of a ferroelectric material; or, At least one of the antiferroelectric layers is composed of an antiferroelectric material.

19. A memory, characterized in that: The memory includes the semiconductor device according to any one of claims 1 to 11.

20. A storage system, characterized in that: The storage system includes a memory and a controller, wherein the controller is coupled to the memory and is used to control the memory to store data; Wherein, the memory comprises the semiconductor device according to any one of claims 1 to 11.

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