Dynamic current sharing method and system for silicon carbide power module

Abstract

The invention discloses a silicon carbide power module dynamic current sharing method and system, and the method comprises the steps: setting a basic layout of a multi-chip parallel silicon carbide power module, and extracting circuit parasitic parameters; setting working conditions of the silicon carbide power module, and setting bus voltage, load current and power chip switching speed; setting the maximum allowable voltage overshoot, and limiting the total capacitance value of the distributed decoupling capacitor bank according to the voltage overshoot; and according to the equivalent impedance of the parallel branches at the set switching speed after the distributed decoupling capacitor bank is added, the capacitance value of the distributed decoupling capacitor is adjusted, so that the equivalent impedance of each branch is the same. By integrating the distributed decoupling capacitors, the problem of non-uniform current distribution in the traditional parallel connection technology is solved, and the method has important theoretical and practical significance for improving the performance of a power electronic system.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a dynamic current sharing method and system for a silicon carbide power module. Background Art

[0002] A power module is a packaged, integrated system consisting of a series of power semiconductor chips, packaged and integrated according to a specific topology, to achieve a specific function. Compared to topologies composed of discrete power chips, power modules are highly integrated and offer significant advantages in electrical and thermal performance, safety, chip lifespan, and cost.

[0003] With the continuous development of semiconductor power chips, driven by increasing environmental requirements in key military and civilian applications such as renewable energy grid integration, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, and pulsed power, as well as the rise of energy conservation and the "dual carbon" slogan, power modules are continuously evolving towards miniaturization, low loss, high power density, high reliability, and high integration. In particular, the emergence of a new generation of wide-bandgap semiconductor chips, represented by silicon carbide and gallium nitride materials, are gradually replacing silicon-based chips in various industrial fields, accelerating the development of power modules. These chips enable power modules to achieve smaller sizes at the same voltage and current levels, operate at higher temperatures, and operate at higher switching frequencies, further reducing the size of passive chips and improving converter efficiency. Power chips, represented by silicon carbide MOSFETs, are expected to replace traditional silicon IGBTs in medium and high-power applications.

[0004] However, silicon carbide chips have a small area and low current capacity, necessitating the parallel connection of multiple silicon carbide chips to enable the power module to pass a high current. During parallel operation, inconsistent circuit parameters can lead to severe current inequality between the parallel chips, resulting in inconsistent chip losses and, consequently, a reduced lifespan of the power module. In silicon carbide power modules, due to their high operating frequency, switching losses contribute significantly to the module's overall performance. Furthermore, the faster switching speeds also lead to greater dynamic current inequality, exacerbating the loss imbalance among the paralleled chips. Furthermore, faster switching speeds also result in higher voltage overshoots, increasing chip switching losses and the risk of overvoltage breakdown in the system, necessitating voltage derating. To address this current balancing issue, current solutions often involve expanding branches with lower parasitic inductance to match those with the highest inductance, thereby achieving current balancing. However, this approach increases the overall module's parasitic inductance, slowing switching speeds, increasing switching losses, and exacerbating voltage overshoots.

[0005] In summary, the use of multi-chip SiC power modules is limited by current sharing and voltage overshoot when multiple chips are connected in parallel, forcing the SiC modules to be used at reduced voltage and current ratings. Therefore, a method is needed to overcome the dynamic current sharing and voltage overshoot issues in multi-chip SiC power modules and efficiently utilize the SiC chips. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art and provide a method and system for dynamic current sharing of a silicon carbide power module. The method adopts the method of inserting a distributed decoupling capacitor group inside the power module to reduce the voltage overshoot during shutdown while weakening the impedance of the parallel high-impedance circuit at high frequency, so that the impedance of the high-impedance circuit in the switching state matches the impedance of the lowest-impedance circuit, thereby achieving efficient dynamic current sharing, which is used to solve the technical problem that the existing multi-chip silicon carbide power module cannot simultaneously achieve efficient dynamic current sharing and reduce voltage overshoot.

[0007] The present invention adopts the following technical solutions: A dynamic current sharing method for a silicon carbide power module, characterized by comprising the following steps: Set up the basic layout of multi-chip parallel SiC power modules and extract circuit parasitic parameters; Set the operating conditions of the silicon carbide power module, including bus voltage, load current, and power chip switching speed; Set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; According to the equivalent impedance of the parallel branches at the set switching speed after the distributed decoupling capacitor group is added, the capacitance value of the distributed decoupling capacitor is adjusted so that the equivalent impedance of each branch is the same.

[0008] Preferably, the parasitic parameters of the extracted circuit include the parasitic inductance of the circuit at a frequency corresponding to the set switching speed, and the parasitic inductance of the external busbar circuit and the busbar capacitor.

[0009] Preferably, the frequency equivalent to the switching speed of the power chip is as follows:

[0010] in, f is the equivalent frequency corresponding to the switching process of the silicon carbide chip, t r is the current rise time.

[0011] Preferably, the voltage overshoot is obtained by circuit simulation, and the peak value of the voltage overshoot after adding the decoupling capacitor is V p1 and V p2 They are:

[0012] in, V DC is the bus voltage peak value, v F_max is the maximum voltage drop of the anti-parallel diode or body diode, L in is the inductance of the power circuit inside the power module, L out is the external loop inductance of the power module, i ds is the current passing through the silicon carbide chip, C 0 is the total capacitance of the decoupling capacitor, I L is the current of the load inductor, Q 1 (0) and Q 2 (0) is the charge amount of the capacitor during the shutdown process.

[0013] Preferably, the charge of the capacitor during the shutdown process Q 1 (0) and Q 2 (0) They are:

[0014] in, t 2 is the time it takes for the voltage to reach the bus voltage, t p1 is the time when the bus voltage reaches the first overshoot peak value, t 3 is the time when the current reaches 0.

[0015] Preferably, the maximum allowable voltage overshoot is the minimum value of the total capacitance of the distributed decoupling capacitors.

[0016] Preferably, the maximum value of the total capacitance of the distributed decoupling capacitors is the point where the first overshoot peak value is equal to the second overshoot peak value.

[0017] Preferably, the equivalent impedance is specifically:

[0018] in, z s1 、 z s2 ... z sn The equivalent source impedances of the 1st to nth silicon carbide chips connected in parallel after adding distributed decoupling capacitors are shown in Figure 2. z s1 '、 z s2 '...z sn ' are the equivalent source impedances of the 1st to nth silicon carbide chips in parallel before adding distributed decoupling capacitors, σ 1... σ n-1 They are the impedance adjustment items after adding distributed decoupling capacitors, and their specific values ​​need to be determined according to the circuit layout.

[0019] Preferably, the impedance imbalance is adjusted by adjusting the capacitance of the distributed decoupling capacitor. δ Minimum impedance imbalance δ The calculation is as follows:

[0020] Among them, max{ z n} is the maximum value of the equivalent source impedance, min{ z n} is the minimum value of the equivalent source impedance, is the average value of the equivalent source impedance.

[0021] In a second aspect, an embodiment of the present invention provides a dynamic current sharing system for a silicon carbide power module, comprising: Extraction module, setting the basic layout of multi-chip parallel silicon carbide power modules and extracting circuit parasitic parameters; Condition module, set the working conditions of silicon carbide power module, set bus voltage, load current, power chip switching speed; The limiting module sets the maximum allowable voltage overshoot and limits the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; The current sharing module adjusts the capacitance value of the distributed decoupling capacitor according to the equivalent impedance of the parallel branch at the set switching speed after the distributed decoupling capacitor group is added, so that the equivalent impedance of each branch is the same.

[0022] In a third aspect, a computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method for dynamic current sharing of silicon carbide power modules when executing the computer program.

[0023] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, comprising a computer program, which, when executed by a processor, implements the steps of the above-mentioned method for dynamic current sharing of a silicon carbide power module.

[0024] In a fifth aspect, a chip comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method for dynamic current sharing of silicon carbide power modules when executing the computer program.

[0025] In a sixth aspect, an embodiment of the present invention provides an electronic device, comprising a computer program, which, when executed by the electronic device, implements the steps of the above-mentioned method for dynamic current sharing of silicon carbide power modules.

[0026] Compared with the prior art, the present invention has at least the following beneficial effects: A dynamic current-sharing method for silicon carbide power modules introduces distributed decoupling capacitors into parallel silicon carbide power modules. Modeling and calculations are used to quickly select the appropriate capacitance of the distributed decoupling capacitors, reducing voltage overshoot while achieving dynamic current sharing for the parallel silicon carbide chips. By precisely controlling the total capacitance of the decoupling capacitors and the distribution ratio of each branch, the voltage can be quickly stabilized when the system is disturbed, significantly reducing voltage overshoot. This protects the silicon carbide power modules from overvoltage damage while improving the overall stability of the system. By optimizing the equivalent impedance of each parallel branch, the parallel silicon carbide chips can achieve balanced switching currents, which not only increases the system's power output capability but also helps reduce device thermal stress and extend device life. This significantly improves the performance and reliability of the power electronics system. By effectively managing and controlling the dynamic behavior of the silicon carbide power modules, they can operate more smoothly at high power output while reducing the potential risk of failure caused by uneven current.

[0027] Furthermore, the parasitic parameters of the circuit are extracted at the frequency corresponding to the set switching speed, including the parasitic inductance of the circuit, the parasitic inductance of the busbar capacitor, etc., so as to perform a complete and accurate modeling of the entire circuit, thereby accurately describing the switching behavior of the circuit under normal working conditions and setting the basic conditions for subsequent optimization. Furthermore, the minimum value of the total capacitance of the distributed decoupling capacitor is set according to the maximum allowable voltage overshoot. Within the range where the decoupling capacitor has a significant impact on the turn-off voltage waveform, setting a larger total capacitance value of the distributed decoupling capacitor can more effectively suppress the voltage overshoot during the turn-off process, and the rated voltage of the components in the circuit will limit the maximum turn-off voltage overshoot amplitude. Therefore, it is necessary to set a total capacitance value of the distributed decoupling capacitor that exceeds the minimum value to ensure the safe operation of the circuit.

[0028] Furthermore, the maximum value of the total capacitance value of the distributed decoupling capacitor is set according to the point where the first overshoot peak value is equal to the second overshoot peak value. After adding the distributed decoupling capacitor with the minimum capacitance value, the two-level peak value presented in the circuit shutdown process is usually reflected in that the second overshoot peak value is much larger than the first overshoot peak value. Within the range exceeding the minimum value, continuing to increase the peak value of the distributed decoupling capacitor will have a greater inhibitory effect on the second overshoot peak value, while having a smaller effect on the first overshoot peak value. When the total capacitance value is increased to the point where the first overshoot peak value is equal to the second overshoot peak value, continuing to increase the total capacitance value will cause the first overshoot peak value to become a voltage peak value during the shutdown process, and will be less affected by the total capacitance value. At this time, the benefit of continuing to increase the capacitance value is not high. Therefore, the maximum value of the total capacitance value of the distributed decoupling capacitor is selected as the point where the first overshoot peak value is equal to the second overshoot peak value.

[0029] It can be understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0030] In summary, the present invention solves the problem of uneven current distribution in traditional parallel technology by integrating distributed decoupling capacitors, which has important theoretical and practical significance for improving the performance of power electronic systems.

[0031] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a layout diagram of a multi-chip silicon carbide power module without distributed decoupling capacitors according to an embodiment of the present invention; Figure 2 This is a layout diagram of a multi-chip silicon carbide power module equipped with distributed decoupling capacitors in an embodiment of the present invention; Figure 3 This is a schematic diagram of the installation of an external busbar circuit and busbar capacitors according to an embodiment of the present invention; Figure 4 It is a step diagram of the method of the present invention; Figure 5 A schematic diagram of a computer device provided in accordance with an embodiment of the present invention; Figure 6 The block diagram of a chip provided according to one embodiment of the present invention is shown.

[0033] Wherein: 101. DC power terminal positive pole; 102. DC power terminal negative pole; 103. AC power terminal; 111. DC power positive pole region; 112. DC power negative pole region; 113. AC power region; 121. First chip upper surface; 122. Second chip upper surface; 123. Third chip upper surface; 124. Fourth chip upper surface; 125. Fifth chip upper surface; 126. Sixth chip upper surface; 201. First upper bridge arm; 202. Second upper bridge arm; 203. Third upper bridge arm; 204. A lower bridge arm; 205. A second lower bridge arm; 206. A third lower bridge arm; 301. A first distributed decoupling capacitor; 302. A second distributed decoupling capacitor; 303. A third distributed decoupling capacitor; 400. A busbar circuit board; 411. A first electrolytic capacitor; 412. A second electrolytic capacitor; 413. A third electrolytic capacitor; 414. A fourth electrolytic capacitor; 415. A fifth electrolytic capacitor; 416. A sixth electrolytic capacitor; 417. A seventh electrolytic capacitor; 418. An eighth electrolytic capacitor; 420. A film capacitor; 430. A connecting circuit board. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] In the description of the present invention, it is to be understood that the terms “include” and “comprise” indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0036] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It should be further understood that the term "and / or" as used in the present specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0038] It should be understood that although the terms "first," "second," and "third" may be used to describe preset ranges in embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are merely used to distinguish one preset range from another. For example, without departing from the scope of embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0039] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0040] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] In modern power electronics systems, silicon carbide (SiC) power modules are widely used due to their high efficiency, high reliability, and high-voltage resistance. In particular, in high-power output applications, multi-chip paralleling has become an effective means of increasing system power capacity. However, in the actual operation of parallel SiC power modules, factors such as differences in device characteristics and inconsistent line impedance often lead to uneven current distribution, which in turn can cause problems such as device overheating, reduced system efficiency, and even equipment damage. Therefore, research on how to achieve dynamic current sharing among parallel SiC power modules is crucial to improving overall system performance.

[0042] The present invention provides a dynamic current balancing method for silicon carbide power modules. Distributed decoupling capacitors are integrated into multi-chip parallel silicon carbide power modules. The method first calculates the required total decoupling capacitor capacitance based on the specific system requirements, such as the maximum allowable voltage overshoot. The voltage overshoot is limited to protect the power module from overvoltage damage and ensure safe system operation. After obtaining the required total decoupling capacitor capacitance, the method determines how to distribute these capacitors to achieve optimal current balancing. The capacitance values ​​are then allocated accordingly to ensure the impedance of each branch is matched as closely as possible, thereby achieving dynamic current balancing. Theoretical analysis and experimental verification demonstrate that the method not only effectively reduces voltage overshoot in silicon carbide power modules, but also enables parallel silicon carbide chips to achieve balanced switching currents, thereby improving the overall performance and reliability of the system.

[0043] See also Figure 1 and Figure 2 The power module used in the present invention is a half-bridge structure with three silicon carbide chips connected in parallel. The power module includes the following parts: A first upper bridge arm 201, a second upper bridge arm 202, a third upper bridge arm 203, a first lower bridge arm 204, a second lower bridge arm 205 and a third lower bridge arm 206; The main power conductive area of ​​the power substrate of the power module is divided into a DC power positive region 111, a DC power negative region 112 and an AC power region 113. The power terminals of the power module include a DC power terminal positive pole 101, a DC power terminal negative pole 102 and an AC power terminal 103; the DC power positive region 111 is connected to the DC power terminal positive pole 101, the DC power negative region 112 is connected to the DC power terminal negative pole 102, and the AC power region 113 is connected to the AC power terminal 103; the first distributed decoupling capacitor 301, the second distributed decoupling capacitor 302 and the third distributed decoupling capacitor 303 are arranged in sequence between the DC power positive region 111 and the DC power negative region 112.

[0044] The first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are spaced apart in the DC power positive region 111, and the first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are connected to the AC power region 113 via the first chip upper surface 121, the second chip upper surface 122 and the third chip upper surface 123 respectively; The first lower bridge arm 204, the second lower bridge arm 205 and the third lower bridge arm 206 are arranged at intervals in the AC power area 113; the first lower bridge arm 204, the second lower bridge arm 205 and the third lower bridge arm 206 are connected to the DC power negative electrode area 112 via the fourth chip upper surface 124, the fifth chip upper surface 125 and the sixth chip upper surface 126 respectively.

[0045] See also Figure 3The external busbar circuit board 400 includes a first electrolytic capacitor 411, a second electrolytic capacitor 412, a third electrolytic capacitor 413, a fourth electrolytic capacitor 414, a fifth electrolytic capacitor 415, a sixth electrolytic capacitor 416, a seventh electrolytic capacitor 417, an eighth electrolytic capacitor 418 and a thin film capacitor 420; the first electrolytic capacitor 411, the second electrolytic capacitor 412, the third electrolytic capacitor 413 and the fourth electrolytic capacitor 414 are connected in series to form a first branch, and the fifth electrolytic capacitor 415, the sixth electrolytic capacitor 416, the seventh electrolytic capacitor 417 and the eighth electrolytic capacitor 418 are connected in series to form a second branch. After the first branch and the second branch are connected in parallel, they are connected to the power module via the thin film capacitor 420 and the connecting circuit board 430.

[0046] See also Figure 4 The present invention provides a dynamic current sharing method for a silicon carbide power module, comprising the following steps: S1. Set up the basic layout of multi-chip parallel silicon carbide power modules and extract circuit parasitic parameters; The parasitic parameters of the extracted circuit mainly include the parasitic inductance of the circuit at the frequency corresponding to the set switching speed, and include the parasitic inductance of the external busbar circuit, busbar capacitor, etc.

[0047] S2. Set the working conditions of the silicon carbide power module, including bus voltage, load current, and power chip switching speed; The frequency equivalent to the switching speed of the power chip of the silicon carbide power module is considered by the following formula:

[0048] in, f is the equivalent frequency corresponding to the switching process of the silicon carbide chip, t r is the current rise time.

[0049] S3. Set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; The number of the distributed decoupling capacitor groups is the same as the number of the parallel silicon carbide chips, and the distributed decoupling capacitor groups are placed close to the parallel silicon carbide chips.

[0050] The voltage overshoot can be obtained through circuit simulation by considering the following formula:

[0051] in, V p1 and V p2 is the peak value of voltage overshoot after adding decoupling capacitor, V DC is the bus voltage peak value, v F_maxis the maximum voltage drop of the anti-parallel diode or body diode, L in is the inductance of the power circuit inside the power module, L out is the external loop inductance of the power module, i ds is the current passing through the silicon carbide chip, C 0 is the total capacitance of the decoupling capacitor, I L is the current of the load inductor, Q 1 (0) and Q 2 (0) is the charge amount of the capacitor during the shutdown process.

[0052] The amount of charge on the capacitor during shutdown Q 1 (0) and Q 2 (0) Consider the following formula:

[0053] in, t 2 is the time it takes for the voltage to reach the bus voltage, t p1 is the time when the bus voltage reaches the first overshoot peak value, t 3 is the time when the current reaches 0.

[0054] The maximum allowable voltage overshoot limit is selected from the minimum value of the total capacitance of the distributed decoupling capacitors. The total capacitance value selected must be greater than this value to limit the voltage overshoot to within the required range.

[0055] The maximum value of the total capacitance of the distributed decoupling capacitor group is recommended to be the point where the first overshoot peak value is equal to the second overshoot peak value. Beyond this point, further adding decoupling capacitors will have limited effect on improving the voltage overshoot.

[0056] The distributed decoupling capacitor group includes but is not limited to ceramic capacitors and silicon chip capacitors.

[0057] S4. According to the equivalent impedance of the parallel branch at the set switching speed after the distributed decoupling capacitor group is added, the capacitance value of the distributed decoupling capacitor is adjusted so that the equivalent impedance of each branch is the same.

[0058] Methods for selecting the distributed decoupling capacitor value with the smallest impedance imbalance include but are not limited to the ergodic method, the gradient descent method, and the neural network method.

[0059] The equivalent impedance mainly refers to the equivalent source impedance which is considered by the following formula:

[0060] in,z s1 、 z s2 ... z sn The equivalent source impedances of the 1st to nth silicon carbide chips connected in parallel after adding distributed decoupling capacitors are shown in Figure 2. z s1 '、 z s2 '... z sn ' are the equivalent source impedances of the 1st to nth silicon carbide chips in parallel before adding distributed decoupling capacitors, σ 1... σ n-1 They are the impedance adjustment items after adding distributed decoupling capacitors, and their specific values ​​need to be determined according to the circuit layout.

[0061] Setting impedance imbalance δ By adjusting the capacitance of the distributed decoupling capacitor to minimize the impedance imbalance, dynamic current sharing and impedance imbalance are achieved. δ Consider the following formula:

[0062] Among them, max{ z n} is the maximum value of the equivalent source impedance, min{ z n} is the minimum value of the equivalent source impedance, is the average value of the equivalent source impedance.

[0063] At this point, the dynamic current sharing of the silicon carbide power module based on distributed decoupling capacitors is achieved by balancing the equivalent source impedance.

[0064] In another embodiment of the present invention, a dynamic current sharing system for a silicon carbide power module is provided. The system can be used to implement the above-mentioned dynamic current sharing method for a silicon carbide power module. Specifically, the dynamic current sharing system for a silicon carbide power module includes an extraction module, a condition module, a restriction module, and a current sharing module.

[0065] Among them, the extraction module sets the basic layout of the multi-chip parallel silicon carbide power module and extracts the circuit parasitic parameters; Condition module, set the working conditions of silicon carbide power module, set bus voltage, load current, power chip switching speed; The limiting module sets the maximum allowable voltage overshoot and limits the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; The current sharing module adjusts the capacitance value of the distributed decoupling capacitor according to the equivalent impedance of the parallel branch at the set switching speed after the distributed decoupling capacitor group is added, so that the equivalent impedance of each branch is the same.

[0066] In one embodiment of the present invention, a terminal device is provided, which includes a processor and a memory, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the dynamic current sharing method of the silicon carbide power module, including: Set up the basic layout of a multi-chip parallel silicon carbide power module and extract circuit parasitic parameters; set the operating conditions of the silicon carbide power module, set the bus voltage, load current, and power chip switching speed; set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; adjust the capacitance value of the distributed decoupling capacitor based on the equivalent impedance of the parallel branch at the set switching speed after adding the distributed decoupling capacitor group, so that the equivalent impedance of each branch is the same.

[0067] See also Figure 5 The terminal device is a computer device. The computer device 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable by the processor 61. When executed by the processor 61, the computer program 63 implements the method for calculating the fluid composition in the reservoir reforming wellbore of the embodiment. To avoid repetition, the details are not described here. Alternatively, when executed by the processor 61, the computer program 63 implements the functions of each model / unit in the dynamic current balancing system of the silicon carbide power module of the embodiment. To avoid repetition, the details are not described here.

[0068] The computer device 60 may be a desktop computer, a notebook computer, a PDA, a cloud server, or other computing devices. The computer device 60 may include, but is not limited to, a processor 61 and a memory 62. It will be understood by those skilled in the art that Figure 5 This is merely an example of the computer device 60 and does not constitute a limitation of the computer device 60 . The computer device 60 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0069] The processor 61 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0070] The memory 62 may be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 may also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device 60.

[0071] Furthermore, the memory 62 may include both an internal storage unit of the computer device 60 and an external storage device. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 may also be used to temporarily store data that has been output or is about to be output.

[0072] See also Figure 6 The terminal device is a chip. The chip 600 of this embodiment includes a processor 622, which may be one or more, and a memory 632 for storing a computer program executable by the processor 622. The computer program stored in the memory 632 may include one or more modules, each corresponding to a set of instructions. In addition, the processor 622 may be configured to execute the computer program to perform the above-mentioned dynamic current sharing method for silicon carbide power modules.

[0073] In addition, the chip 600 may further include a power supply component 626 and a communication component 650. The power supply component 626 may be configured to perform power management of the chip 600, and the communication component 650 may be configured to implement communication, such as wired or wireless communication, of the chip 600. In addition, the chip 600 may further include an input / output interface 658. The chip 600 may operate based on an operating system stored in the memory 632.

[0074] In another embodiment of the present invention, the present invention further provides a storage medium, specifically a computer-readable storage medium, which is a memory device in a terminal device for storing programs and data. It can be understood that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and, of course, the extended storage medium supported by the terminal device. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space. These instructions can be one or more computer programs. It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory (Non-Volatile Memory), such as at least one disk memory.

[0075] The processor may load and execute one or more instructions stored in a computer-readable storage medium to implement the corresponding steps of the method for dynamic current sharing of a silicon carbide power module in the above embodiment; the processor may load and execute the following steps: Set up the basic layout of a multi-chip parallel silicon carbide power module and extract circuit parasitic parameters; set the operating conditions of the silicon carbide power module, set the bus voltage, load current, and power chip switching speed; set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group based on the voltage overshoot; adjust the capacitance value of the distributed decoupling capacitor based on the equivalent impedance of the parallel branch at the set switching speed after adding the distributed decoupling capacitor group, so that the equivalent impedance of each branch is the same.

[0076] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0077] Example 1. Basic layout and parasitic parameter extraction The basic layout of a multi-chip parallel silicon carbide power module was set up, and circuit parasitic parameters were extracted. The circuit parasitic parameters in this embodiment were extracted, and the module external inductance was extracted to be 57.8nH, and the longest commutation loop inductance inside the module was 18.66nH.

[0078] 2. Working condition settings Set the operating conditions of the SiC power module, including bus voltage, load current, and power chip switching speed. Here, the bus voltage is set to 400V; the load current is set to 90A, meaning the current on each chip is 30A; and the chip turn-on time is set to 20ns.

[0079] 3. Allowable voltage overshoot Set the maximum allowable voltage overshoot and select the total capacitance value of the distributed decoupling capacitors based on the voltage overshoot limit. Here, the maximum allowable voltage overshoot is set to 15%, which means the maximum voltage limit is 460V. Using simulation or model calculations, the minimum allowable total decoupling capacitor value is 100nF. When the total decoupling capacitor value is 250nF, the calculated two voltage overshoot peaks are equal, which is set as the maximum decoupling capacitor value. The final decoupling capacitor value is 150nF.

[0080] 4. Equivalent impedance adjustment Based on the module layout, three sets of distributed decoupling capacitors were added to the three parallel SiC chips. The equivalent impedance of the parallel branches at the set switching speed was then determined by selecting the capacitance values ​​of the distributed decoupling capacitors to ensure the same equivalent impedance across all branches. By modeling the impedance at the frequency corresponding to the set switching speed, with a current imbalance of less than 2.5% as the adjustment target, the final three sets of distributed decoupling capacitors were selected, with values ​​of 50nF, 30nF, and 70nF.

[0081] 5. Effect evaluation Voltage overshoot limitation: After adopting the method of the present invention, the voltage overshoot is limited from 43.5% to 14.5%; Dynamic current imbalance: Dynamic current imbalance is limited from 47.5% to 0.9%; Loss reduction: The method of the present invention can significantly reduce dynamic current imbalance while limiting voltage overshoot, reduce the loss of parallel silicon carbide chips and achieve balanced switching losses.

[0082] In summary, the present invention provides a dynamic current equalization method and system for silicon carbide power modules, which utilizes the limiting condition of the maximum voltage overshoot amplitude to obtain the total capacitance of the decoupling capacitor, and determines the capacitance of the distributed decoupling capacitor based on the equivalent impedance matching of the parallel branches. While reducing the voltage overshoot of the silicon carbide power module, the parallel silicon carbide chips can obtain balanced switching current.

[0083] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0084] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0085] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0086] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, and can be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0089] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0090] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0093] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A dynamic current sharing method for a silicon carbide power module, characterized in that: The following steps are involved: Set up the basic layout of multi-chip parallel SiC power modules and extract circuit parasitic parameters; Set the working conditions of the silicon carbide power module, set the bus voltage, load current, and power chip switching speed; Set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot; According to the equivalent impedance of the parallel branches at the set switching speed after the distributed decoupling capacitor group is added, the capacitance value of the distributed decoupling capacitor is adjusted so that the equivalent impedance of each branch is the same.

2. The dynamic current balancing method for silicon carbide power module according to claim 1, characterized in that: The parasitic parameters of the extracted circuit include the parasitic inductance of the circuit at the frequency corresponding to the set switching speed, and the parasitic inductance of the external busbar circuit and busbar capacitor.

3. The dynamic current sharing method for silicon carbide power module according to claim 1, characterized in that: The equivalent frequency corresponding to the switching process of the silicon carbide chip is as follows: in, t r is the current rise time.

4. The dynamic current sharing method for silicon carbide power module according to claim 1, characterized in that: The voltage overshoot is obtained through circuit simulation, and the peak value of the voltage overshoot after adding the decoupling capacitor V p1 and V p2 They are: in, V DC is the bus voltage peak value, v F_max is the maximum voltage drop of the anti-parallel diode or body diode, L in is the inductance of the power circuit inside the power module, L out is the external loop inductance of the power module, i ds is the current passing through the silicon carbide chip, C 0 is the total capacitance of the decoupling capacitor, I L is the current of the load inductor, Q 1 (0) and Q 2 (0) is the charge amount of the capacitor during the shutdown process.

5. The dynamic current sharing method for silicon carbide power module according to claim 4, characterized in that: The amount of charge on the capacitor during shutdown Q 1 (0) and Q 2 (0) They are: in, t 2 is the time it takes for the voltage to reach the bus voltage, t p1 is the time when the bus voltage reaches the first overshoot peak value, t 3 is the time when the current reaches 0.

6. The dynamic current sharing method for silicon carbide power module according to claim 1, characterized in that: The maximum allowable voltage overshoot is the minimum value of the total capacitance of the distributed decoupling capacitors.

7. The method for dynamic current sharing of silicon carbide power module according to claim 6, characterized in that: The maximum value of the total capacitance of the distributed decoupling capacitor is the point where the first overshoot peak value is equal to the second overshoot peak value.

8. The dynamic current sharing method for silicon carbide power module according to claim 1, characterized in that: The equivalent impedance is: in, z s1 , z s2 ... z sn They are the equivalent source impedances of the 1st to nth silicon carbide chips connected in parallel after adding distributed decoupling capacitors, z s1 '、 z s2 '... z sn ' are the equivalent source impedances of the 1st to nth silicon carbide chips connected in parallel before adding distributed decoupling capacitors, σ 1... σ n-1 They are impedance adjustment items after adding distributed decoupling capacitors, and their specific values ​​need to be determined according to the circuit layout.

9. The dynamic current balancing method for silicon carbide power module according to claim 8, characterized in that: By adjusting the capacitance of the distributed decoupling capacitor, the impedance imbalance δ Minimum, impedance imbalance δ The calculation is as follows: Among them, max{ z n } is the maximum value of the equivalent source impedance, min{ z n } is the minimum value of the equivalent source impedance, is the average value of the equivalent source impedance.

10. A dynamic current sharing system for a silicon carbide power module, characterized in that: include: Extraction module, setting the basic layout of multi-chip parallel SiC power modules and extracting circuit parasitic parameters; Condition module, set the working conditions of silicon carbide power module, set bus voltage, load current, power chip switching speed; A limiting module sets the maximum allowable voltage overshoot and limits the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot; The current sharing module adjusts the capacitance value of the distributed decoupling capacitor according to the equivalent impedance of the parallel branch at the set switching speed after the distributed decoupling capacitor group is added, so that the equivalent impedance of each branch is the same.

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