Data error correction method based on BCH coding, storage medium and integrated chip

Abstract

The invention discloses a data error correction method based on BCH coding, a storage medium and an integrated chip, and relates to the technical field of chip design and application, the data error correction method based on BCH coding comprises the following steps: obtaining target data obtained by BCH coding, and according to a target vector of the target data and a preset check matrix, correcting the target vector of the target data; determining each syndrome corresponding to the target vector; if the syndromes representing data errors exist in the determined syndromes, generating an error equation according to the syndromes; constructing a target number of verification equations based on the coefficient of the error equation, grouping the constructed verification equations, and solving each group of verification equations by adopting the same group of summation modules to obtain error position data; and performing error correction on the target data according to the error position data to obtain an error correction result. By applying the scheme provided by the embodiment of the invention, resources occupied for realizing the error correction function can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip design and application technology, and in particular to a data error correction method, storage medium and integrated chip based on BCH coding. Background Art

[0002] In the process of decoding the data encoded by BCH (Bose-Chaudhuri-Hocquenghem), error correction requires the most computational effort compared to simple error detection, especially when a large number of data bits are transmitted simultaneously. Existing technologies often design a large number of complex circuits to complete the calculation within one clock cycle, or insert registers to form a pipeline. Although this can reduce path delays, the actual circuit area does not decrease.

[0003] In actual chip applications, not every data transmission will go wrong. For example, in the flash memory, the probability of error is actually very low in the early stage of device use. The error detection function needs to be used every time data is transmitted, while the error correction function is only used after an error is detected. However, the error correction circuit is much more complicated than the error detection circuit. In order to realize the error correction function, the BCH circuit designed in the prior art occupies a large area of ​​the chip, and the resource utilization efficiency is low. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least some extent. To this end, one object of the present invention is to provide a data error correction method, storage medium and integrated chip based on BCH coding to reduce the resources occupied by the error correction function.

[0005] According to a first aspect of an embodiment of the present invention, a data error correction method based on BCH coding is provided, the method comprising: Obtain target data obtained by BCH encoding, and determine each syndrome corresponding to the target vector according to a target vector of the target data and a preset check matrix; wherein the target vector is obtained by splicing the target data and the check bit data corresponding to the target data; If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to the syndromes; Constructing a target number of check equations based on the coefficients of the error equation, wherein the target number is consistent with the number of bits of the target vector; The constructed verification equations are grouped, and each group of verification equations is solved using the same group of summing modules to obtain error position data; wherein each summing module in the same group of summing modules includes a modular multiplier and a modular adder; The target data is corrected according to the error position data to obtain an error correction result.

[0006] According to a second aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned data error correction method based on BCH coding is implemented.

[0007] According to a third aspect of an embodiment of the present invention, an integrated chip is provided, comprising: a memory and a processor; a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned data error correction method based on BCH coding is implemented.

[0008] In the solution provided by the embodiment of the present invention, each syndrome corresponding to the target vector is determined according to the target vector of the target data and a preset check matrix. The syndrome can be used to determine whether there is a data error. If so, the syndrome is used to generate an error equation, and then a check equation is constructed based on the error equation to obtain error position data, thereby determining the error position and performing error correction.

[0009] In the process of solving the check equation, the check equation is grouped and the same group of summing modules is reused for solving. In this way, there is no need to design a summing module and a corresponding circuit separately for each check equation. By reusing the modular multipliers and modular adders in the summing module, the area of ​​the BCH error correction circuit can be greatly reduced, thereby improving resource utilization efficiency.

[0010] And if no error is detected, the calculation based on the syndrome can give data in a shorter time. If error correction is required, the correct result can also be given within fewer clock cycles.

[0011] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flowchart of a data error correction method based on BCH coding provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of a first circuit structure provided by an embodiment of the present invention; Figure 3 is a schematic diagram of a second circuit structure provided by an embodiment of the present invention; Figure 4 is a schematic diagram of a third circuit structure provided by an embodiment of the present invention; Figure 5 is a state transition diagram of a state machine provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of a fourth circuit structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0014] The following describes a data error correction method, a storage medium, and an integrated chip based on BCH coding according to an embodiment of the present invention with reference to the accompanying drawings.

[0015] In one embodiment of the present invention, see Figure 1 , provides a data error correction method based on BCH coding, including the following steps S101-S105.

[0016] S101: Obtain target data obtained by BCH coding, and determine syndromes corresponding to the target vector according to a target vector of the target data and a preset check matrix.

[0017] The target vector is obtained by concatenating the target data and the check bit data corresponding to the target data.

[0018] S102: If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to each syndrome.

[0019] S103: constructing a target number of check equations based on the coefficients of the error equation, where the target number is consistent with the number of bits of the target vector.

[0020] S104: Grouping the constructed verification equations, and solving each group of verification equations using the same group of summation modules to obtain error position data.

[0021] Each summing module in the same group of summing modules includes a modular multiplier and a modular adder.

[0022] S105: Correct the target data according to the error position data to obtain an error correction result.

[0023] The target data and check bit need to be generated by using a coding module of a BCH code. The implementation method of generating the target data and check bit by BCH coding is an existing method in the prior art and will not be described in detail here.

[0024] Assume that the target data has n bits and the check bits have r bits, which are spliced ​​together to generate a target vector of n+r bits. Correspondingly, there are also n+r check equations.

[0025] This application can use shortened or unshortened BCH codes. Assuming the total codeword length is N, the maximum number of correctable bits is t, the number of parity bits is r, and the number of data bits to be decoded is n, where n <= N - r. When n < N - r, it is a shortened BCH code. In this case, it can be padded with 0s at the high bits to make it N - r bits and the above error correction method can be implemented.

[0026] As Figure 2 shown in the circuit structure schematic diagram, data_dcd_i represents the target data, and parity_dcd_i represents the parity bit data; the target vector is input to the syndrome generation module to obtain t syndromes S 1 , S 3 ,... S 2t-1 .

[0027] If all the values of the syndromes are 0, it means there is no error. The state machine outputs a high - level signal on the dcd_done pin and outputs the decoded data data_dcd_o and parity bit data parity_dcd_o included in the error correction result. Among them, data_dcd_o = data_dcd_i and parity_dcd_o = parity_dcd_i.

[0028] If the calculated syndromes are not all 0, it means there are data errors and error correction is required.

[0029] In one embodiment, the syndromes can be determined according to the following formula:

[0030] where S represents each syndrome; d represents the target vector; represents the parity - check matrix; The parity - check matrix is:

[0031] where H represents the parity - check matrix; represents the element in, m is a preset parameter; t represents the number of syndromes; n represents the number of bits of the target data; r represents the number of bits of the parity - bit data.

[0032] GF (Galois Field) is a set containing a finite number of elements, and these elements are closed under addition and multiplication operations. Specifically, is a finite field, and the elements are polynomials including 0 and 1. In this set, the results of addition and multiplication operations are still in this set.

[0033] Specifically, in the H matrix, any It can be represented as an m-dimensional vector, where i can be any integer from 0 to (2t-1)(n+r-1). Replace each element of H with its corresponding The m-dimensional vector on the field and expressed in column form can obtain the transposed matrix of the binary check matrix, which has a total of mt columns, n+r rows, and each column is a column vector.

[0034] Then the syndrome is equal to the target vector d multiplied by the transpose of the check matrix H: The obtained S is a vector of mt dimensions, consisting of t syndromes: S=[S 1 , S 3 , ... S 2t-1 ], where each syndrome is An m-dimensional vector over the field.

[0035] According to the above principle, the column vectors composed of the column elements in the transposed matrix of the check matrix can be determined; for each column vector, a syndrome element is determined according to the column vector and the target vector; and each syndrome is generated based on the determined syndrome element.

[0036] Furthermore, different column vectors can be stored in different branches of the parallel circuit. The hardware can be used as follows Figure 3 The circuit of the structure shown calculates the syndrome S. The modular addition of binary elements is actually an XOR operation. A0, A1, A2...A(mt-1) are column vectors composed of the 1st, 2nd, 3rd...column elements after the check matrix is ​​transposed. In this way, each column vector can be calculated in parallel.

[0037] Multiplying the input vector d with a total of n+r bits and the corresponding elements in A0 one by one and then performing bit-wise XOR operation on them is equivalent to performing an operation on {data_dcd_i, parity_dcd_i} and A[0] in the figure. The result is the lowest-order element S[0] of the syndrome. Similarly, according to this method, performing the above operation on the target vector and A1 can obtain S[1]. Similarly, S[2], S[3], and so on are calculated until S[mt-1]. Performing the above operation on the target vector and A2 can obtain S[2]. There are a total of mt such circuits, corresponding to a set of syndromes S with an output of mt bits.

[0038] Specifically, the error equation can be generated according to the following formula: :

[0039] in, , , ,……, are the coefficients of the error equation, and v represents the number of error correction bits; the coefficients of the error equation are determined based on the accompanying equations.

[0040] Among them, for domain, the maximum correctable number of digits t is ( ) / 2 is a positive number rounded down, v<=t.

[0041] like Figure 2 As shown, the syndrome generation module gives the syndrome to the error equation generation module, and the error equation generation module calculates the error equation The coefficients of .

[0042] The error equation generation module only involves modular multiplication and modular addition operations. This part of the circuit is all combinational logic, which can calculate the coefficients within one clock cycle and send them to the money search module. And because the column vector is based on Figure 3 The circuits can be calculated separately and simultaneously without going through any sequential circuits, so they can be completed within one clock cycle, greatly saving decoding time.

[0043] The relationship between and the syndrome S is given by the following Newton identity:

[0044]

[0045] The money search module applies Peterson decoding theory and constructs n+r check equations according to the coefficients of the error equation, corresponding to the n+r bits of the decoded data and the check bit data that need to be corrected.

[0046] After the check equations are grouped, each group of check equations is input into the same group of summation modules checksum_0, checksum_1, checksum_2, ..., checksum_u-1 for solution, thereby reducing the area of ​​the BCH error correction circuit through multiplexing.

[0047] During the operation of the money search module, the state machine controls the operation state and controls the high level signal output by the dcd_done pin after the operation is completed.

[0048] In the solution provided by the embodiment of the present invention, each syndrome corresponding to the target vector is determined according to the target vector of the target data and a preset check matrix. The syndrome can be used to determine whether there is a data error. If so, the syndrome is used to generate an error equation, and then a check equation is constructed based on the error equation to obtain error position data, thereby determining the error position and performing error correction.

[0049] In the process of solving the check equation, the check equation is grouped and the same group of summing modules is reused for solving. In this way, there is no need to design a summing module and a corresponding circuit separately for each check equation. By reusing the modular multipliers and modular adders in the summing module, the area of ​​the BCH error correction circuit can be greatly reduced, thereby improving resource utilization efficiency.

[0050] And if no error is detected, the calculation based on the syndrome can give data in a shorter time. If error correction is required, the correct result can also be given within fewer clock cycles.

[0051] The following describes the calculation process using the calibration equation.

[0052] In one embodiment, among the target number of verification equations, the i-th verification equation is constructed as:

[0053] in, , , ,……, is the coefficient of the error equation, v represents the number of error correction bits; express Medium element.

[0054] For any bit i, the corresponding check equation is the sum of multiple additions, that is, the checksum. If the value of the checksum is It is 0, indicating that the Ni-th bit is wrong, N represents the code length, otherwise it is 1.

[0055] Each check equation needs to perform v modular multiplication and modular addition calculations. When the number of bits n+r that need to be corrected is relatively large, the amount of calculation is also quite large. If all are implemented by combinational logic, the scale of the circuit occupied will be relatively large. Therefore, the solution provided in the embodiment of the present invention groups the check equations, reuses modular multipliers and modular adders, performs one calculation per clock cycle, and completes the calculation of all check equations in several clock cycles. This can greatly reduce the number of modular multipliers and modular adders, thereby reducing the circuit scale and area. Although several clock cycles will be added, as mentioned above, in most cases in actual use, error correction is not required, only error detection is required, and the error detection operation can be completed within one clock cycle using the syndrome generation module introduced above, so the loss of performance is very small.

[0056] like Figure 2 As shown in , checksum_0, checksum_1, checksum_2, ..., checksum_u-1 are a group of summation modules, which contain a total of u summation modules. Figure 4As shown, each checksum module includes a modular multiplier and a modular adder, and the modular adder is represented by the symbol "+".

[0057] In addition, each summing module may also include a register; For each summing module, a target check equation to be solved is selected from each set of check equations through a first selection signal; the target check equation is solved using the summing module in the following manner: For the nth modular multiplication calculation included in the target verification equation, the modular multiplier included in the summing module is used to obtain an intermediate calculation result, and the intermediate calculation result is subjected to modular addition calculation with the modular addition calculation result stored in the register to obtain the nth modular addition calculation result, and the nth modular addition calculation result is used to update the modular addition calculation result stored in the register; After completing all modular multiplication calculations contained in the target verification equation, the solution result of solving the target verification equation is obtained from the register, that is, Figure 4 in error_map.

[0058] exist Figure 4 In , group_select indicates that the first selection signal is used to select a group of check equations as the target check equations for calculation. Each time a group of u check equations is selected, different summation modules determine the target check equations according to the order of arrangement of the check equations. For example, for the summation module checksum_0, the first check equation in each group of u check equations is selected as the target check equation; for the summation module checksum_1, the second check equation in each group of u check equations is selected as the target check equation, and so on.

[0059] According to the above method, starting from n=1, after the result of the nth operation is stored in the register, if there is an n+1th modular multiplication calculation, the intermediate result of the n+1th modular multiplication calculation is obtained, and then the modular addition calculation is performed with the previous calculation result in the register to cover the calculation result previously stored in the register, and so on. After completing all modular multiplication calculations, the register contains the sum of all modular multiplication calculation results.

[0060] The specific value of u is adjusted according to the size of the verification equation grouping. For example, if every 4 verification equations are grouped together, then u = 4 summation modules can be set. In this way, when designing a chip, the number of modular multipliers and modular adders and the number of clock cycles can be flexibly configured according to the actual application scenario, and the best solution can be selected by weighing the area and performance.

[0061] Assume that n+r verification equations are divided into w groups, each group contains u equations, the first u equations are calculated, the second time the u+1 to 2u equations are calculated, and so on.

[0062] exist Figure 4 In the example, after the group_select signal selects the group of the check equation, the ckst signal is used to select a modular multiplication calculation in the check equation. For example, select α(i) and transmit it to the error equation generation module 1 is sent to the modular multiplier, the result is XORed with the result of the previous modular multiplication, and then stored in the register, and then α (2i) and 2 Perform modular multiplication, XOR the result of modular multiplication with the result stored in the register and store it in the register, continue to overwrite the previous XOR calculation result until α (vi) and The modular multiplication of v is performed, and the modular multiplication result is XORed with the XOR result in the register to obtain a solution to the verification equation.

[0063] Figure 4 where α(i), α(2i)…α(vi) are equivalent to the ith verification equation in the above , ,…… σ1, σ2, ... σv are equivalent to , , ,……, .

[0064] Then, the group_select signal is used to select the calculation of the target calibration equation in the next set of calibration equations. The elements of the next target calibration equation are α(i+u), α(2(i+u))... The calculation method is similar to the above α(i), α(2i)... until the last set of target calibration equations is calculated.

[0065] Repeating this process v times can complete the calculation of a verification equation.

[0066] Each summation module repeats the above process w times, and finally the error_map containing the error position, i.e., the error position data, can be obtained.

[0067] Because w groups are divided, the Qian search module needs vw clock cycles to complete a search for an error position, where v is the number of error correction bits. For example, if two bits are corrected and calculated in four groups, a total of 2*4=8 clock cycles are required, and the number of modular multipliers and modular adders required is only 1 / 8 of the original number, which greatly optimizes the circuit area of ​​the Qian search module. Using this method, different grouping methods can be freely selected according to actual needs. For example, in the case of high performance requirements, if there are many check equations, the number of u can be increased to reduce the number of groups, so that multiple check equations can be solved simultaneously in the same clock cycle, reducing the number of clock cycles required for calculation. In the case of high area requirements, the number of modular multipliers and modular adders can also be reduced by increasing the number of groups.

[0068] It can be seen from the above embodiment that the n+r check equations respectively correspond to the n+r bit positions that need to be corrected.

[0069] In this way, for each bit, the value of the check equation can be obtained, so that the sequence of n+r bit positions forms a corresponding checksum sequence, in which the position where 0 is located represents the error position.

[0070] In this case, a checksum sequence representing the error position in the error position data may be obtained; an XOR calculation is performed on the inverted result of the checksum sequence and the target data to obtain an error correction result.

[0071] That is, the checksum sequence is first inverted, that is, 0 at any position is replaced by 1, and 1 is replaced by 0. The inverted result is XORed with the target data to obtain the error-corrected data.

[0072] The following instructions Figure 5 The embodiment shown illustrates the control process of the state machine in the aforementioned embodiment.

[0073] The state machine is used to control the calculation process of the money search module and output the decoding completion signal dcd_done.

[0074] First, the state machine generates a flag signal error_flag according to the syndrome S given by the syndrome generation module. If all the syndromes S are equal to 0, it means that no error is detected, error_flag=0; otherwise error_flag=1.

[0075] The number of states of the state machine is equal to the number w of check equation groups. Among the w states, different states represent the selection of different groups of check equations among the w groups of check equations. Figure 5 In the CKST signal, the ckst signal is used to control the number of modular multiplication operations performed by each summation module in the current group, and is automatically increased by 1 in each cycle.

[0076] Taking w = 4 as an example, its state transition diagram is as follows Figure 5 shown. When error_flag is equal to 0, no error correction is required and the state machine does not make any jumps. If error_flag is not equal to 0, ckst starts counting, and the money search module starts calculating the first set of parity equations. When ckst reaches the number of modular multiplications v in the parity equation, ckst < v does not hold. At this time, when the conditions ckst = v and error_flag = 1 are met, the state machine jumps from Group1 (idle state) to Group2, calculates the second set of parity equations, and at the same time the money search module starts calculating the second set of parity equations. This process continues in turn. In Group2, Group3, and Group4, ckst < v means that not all modular multiplications have been calculated, and when ckst = v, it jumps to the next state.

[0077] Until the last set of calculations is completed, the state machine returns to the initial Group1 state, and at the same time outputs the fsm_done signal indicating that the calculation is completed.

[0078] The output of the signal dcd_done indicating the completion of decoding can be implemented through the following logic circuit, as shown in Figure 6 .

[0079] When the signal dcd_en indicating the start of decoding is 1, if the flag signal error_flag generated according to the syndromes s[0]... s[mt - 1] is equal to 0, that is, there is no error, then dcd_done directly outputs 1 indicating the completion of decoding. If error_flag is not equal to 0, then after the money search module finishes the calculation and fsm_done outputs 1, dcd_done will be 1. At this time, the corrected data can be obtained from the output port of the decoding module.

[0080] In an embodiment of the present invention, there is also provided a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the data error correction method based on BCH coding described in any one of the foregoing.

[0081] In an embodiment of the present invention, there is also provided an integrated chip. The chip is integrated with a circuit, and the circuit is used to execute the data error correction method based on BCH coding described in any one of the foregoing.

[0082] Designing each item of the BCH circuit in the foregoing embodiments is suitable for application in high-bandwidth, multi-bit error correction, and small-area semiconductor chips, especially in embedded system MCUs with relatively high requirements for information reliability.

[0083] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0084] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0085] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0086] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0087] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0088] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0089] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0090] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data error correction method based on BCH coding, characterized in that: The method comprises: Obtain target data obtained by BCH encoding, and determine each syndrome corresponding to the target vector according to a target vector of the target data and a preset check matrix; wherein the target vector is obtained by splicing the target data and the check bit data corresponding to the target data; If there is a syndrome indicating data error among the determined syndromes, an error equation is generated according to the syndromes; Constructing a target number of check equations based on the coefficients of the error equation, wherein the target number is consistent with the number of bits of the target vector; The constructed verification equations are grouped, and each group of verification equations is solved using the same group of summing modules to obtain error position data; wherein each summing module in the same group of summing modules includes a modular multiplier and a modular adder; The target data is corrected according to the error position data to obtain an error correction result.

2. The method according to claim 1, characterized in that The determining, according to the target vector of the target data and a preset check matrix, each syndrome corresponding to the target vector comprises: Determine each syndrome according to the following formula: Wherein, S represents each syndrome; d represents the target vector; represents the check matrix; The check matrix is: Wherein, H represents the check matrix; express In the element, m is a preset parameter; t represents the number of syndromes; n represents the number of bits of the target data; and r represents the number of bits of the check bit data.

3. The method according to claim 2, characterized in that Determine the syndromes as follows: Determine a column vector composed of column elements in a transposed matrix of the check matrix; For each column vector, a syndrome element is determined according to the column vector and the target vector; Syndromes are generated based on the determined syndrome elements.

4. The method according to claim 3, characterized in that Different column vectors are stored in different branches of the parallel circuit.

5. The method according to claim 1, characterized in that The error equation is generated as follows : in, ……、 are the coefficients of the error equation, and v represents the number of error correction bits; the coefficients of the error equation are determined according to each syndrome.

6. The method according to claim 5, characterized in that Among the target number of verification equations, the i-th verification equation is constructed as: in, ……、 is the coefficient of the error equation, and v represents the number of error correction bits; express Medium element.

7. The method according to claim 1, characterized in that Each of the summing modules also includes a register; For each summing module, a target verification equation to be solved is selected from each group of verification equations through a first selection signal; The target verification equation is solved using the summation module in the following manner: For the nth modular multiplication calculation included in the target verification equation, an intermediate calculation result is obtained by using the modular multiplier included in the summation module, and the intermediate calculation result is subjected to modular addition calculation with the modular addition calculation result stored in the register to obtain the nth modular addition calculation result, and the nth modular addition calculation result is used to update the modular addition calculation result stored in the register; After completing all modular multiplication calculations included in the target verification equation, a solution result of solving the target verification equation is obtained from the register.

8. The method according to claim 1, characterized in that The step of correcting the target data according to the error position data to obtain an error correction result includes: Acquire a checksum sequence representing an error position in the error position data; An XOR calculation is performed on the inverted result of the checksum sequence and the target data to obtain an error correction result.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data error correction method based on BCH coding as described in any one of claims 1 to 8 is implemented.

10. An integrated chip, characterized in that: A circuit is integrated on the chip, and the circuit is used to execute the data error correction method based on BCH coding as described in any one of claims 1-8.

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