Delayed memory access request arbitration

Abstract

A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller (102) and dispatching a second memory access request to the memory controller (102) in response to an anticipated completion of a memory access operation represented by the first memory access request. Another method includes receiving a first memory access request at a bus interface unit (106) at a first time, dispatching a second memory access request to a memory controller (102) at a second time subsequent to the first time, receiving a third memory access request at the bus interface unit (106) at a third time subsequent to the second time, dispatching the third memory access request to the memory controller (102) at a fourth time subsequent to the third time and dispatching the first memory access request to the memory controller (102) at a fifth time subsequent to the fourth time.

Description

technical field [0001] The present invention generally relates to processing memory access requests. Background technique [0002] Memory controllers are often used in processing systems to control access to memory resources for devices seeking to store data in memory or access data from memory. In conventional systems, memory access requests are supplied to the memory controller once when the memory controller is available to receive memory access requests. The memory controller then typically buffers the memory access requests and processes the buffered memory access requests according to some specified priority. However, due to the known technique of dispatching memory access requests to the memory controller once the memory controller is able to buffer or process the next memory access request, if certain higher priority memory access requests become available to the memory controller for the first time The next memory access request became valid for selection, but the...

AI Technical Summary

Problems solved by technology

However, due to the known technique of dispatching memory access requests to the memory controller once the memory controller is able to buffer or process the next memory access request, if certain higher priority memory access requests become available to the memory controller for the first time The selection became valid after the next memory access request, but the requests were not processed in the most efficient manner

As an illustration, the processing of a higher priority memory access request in the event that a higher priority memory access request is received briefly after a lower priority memory access request is dispatched due to the availability of the next request received by the memory controller May be delayed until the memory controller is again able to accept the next memory access request

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