Multi-hardware thread processor and business processing method thereof

Abstract

The embodiment of the invention discloses a multi-hardware thread processor and a business processing method thereof. The method comprises the following steps: obtaining the FIFO queue status of hardware thread and transmitting a control command to an upstream hardware thread when the FIFO queue status reaches a preset status, wherein the upstream hardware thread receiving the control command processes business according to the control command. The thread processor comprises a hardware thread and at least one upstream hardware thread of the hardware thread. The hardware thread can transmit the control command to the upstream hardware thread according to the self FIFO queue status so that the upstream hardware thread suspends the business processing, the utilization rate of production lineresources occupied by various hardware threads can be effectively improved, the waste of production line resources is reduced and the performance for the whole CPU to process business is improved.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a multi-hardware thread processor and a business processing method thereof. Background technique [0002] In a multi-core multi-hardware thread processor (CPU), a CPU core usually contains a pipeline and multiple concurrently running hardware threads, where each hardware thread has its own context, registers, interrupts, and exception handling , the operating system or application software runs on this hardware thread, just like running on a CPU, so this hardware thread is also called a virtual CPU (virtual CPU, vCPU). Since multiple hardware threads share one pipeline, although the performance of the pipeline can be maximized, if one hardware thread occupies too many pipeline resources, the performance of other hardware threads will inevitably be reduced, so it is necessary to control the resources occupied by each hardware thread of the pipeline , improve the overall perform...

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Problems solved by technology

[0004] In the process of realizing the present invention, the inventor finds that the prior art has at least the following defects: because a business process requires multiple hardware threads on a CPU core to complete , such as the packet processing of a firewall, and when multiple hardware threads of the CPU core are processing the same business process, the upstream hardware thread that executes the previous business process is handed over to the downstream hardware thread to continue processing after the message is processed. If the downstream hardware thread is too busy to process, and the message needs to be discarded, the resources of the pipeline occupied by the upstream hardware thread executing the previous business process will be wasted, thus reducing the performance of the entire CPU to process business.

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