Peak valley power utilization timer

An electric timer and peak-valley technology, which is applied in the field of peak-valley electric timers, can solve the problem of idle power in the power grid, and achieve the effects of reducing the cost of electricity consumption, balancing the power consumption of the power grid, and being convenient to use.

Inactive Publication Date: 2011-02-16
苏州高新区禾云设备设计事务所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the power of the power grid during the valley period is generally idle.

Method used

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  • Peak valley power utilization timer
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Embodiment Construction

[0014] The technical implementation process of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0015] see figure 1 As shown, a peak and valley power consumption timer includes a programmable control chip U1, which also includes NAND gates U2, U3 and U4, and an input end of the NAND gate U2 is connected to the programmable control chip U1 An output terminal A of the NAND gate U2, the other input terminal of the NAND gate U2 is connected to the output terminal of the NAND gate U3, and an output terminal of the NAND gate U3 is connected to the other output terminal of the programmable control chip U1 Terminal B, the other output end of the NAND gate U3 is connected to the output end of the NAND gate U2 to form a common output end; the two input ends of the NAND gate U4 are connected together to form a common input end; the common output connected to the common input terminal, the output terminal of the NAND g...

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Abstract

The invention discloses a peak valley power utilization timer. The timer comprises a programmable control chip U1, a nand gate U2, a nand gate U3 and a nand gate U4, wherein a point A of the programmable control chip U1 triggers a trigger consisting of the nand gate U2 and the nand gate U3 to supply power to the timer; and a point B of the programmable control chip U1 triggers a trigger consisting of the nand gate U2 and the nand gate U3 to cut off the power of the timer. Trigger moments of the point A and the point B of the programmable control chip U1 are programmed in the programmable control chip U1 and an operating interface can be arranged. In application, the peak valley power utilization timer can be made into the independent peak valley power utilization timer, or the timer of the invention can be embedded into a household appliance, so that the household appliance can be used at night. Through the timer, the power used in a valley period at night is increased, so that the power consumption of a power grid is more balanced.

Description

technical field [0001] The invention relates to a timer, in particular to a peak-valley electricity consumption timer. Background technique [0002] Today's home appliances operate on demand. This demand is often within the time period of normal life, that is, during peak hours. Therefore, the power of the power grid during the valley period is generally idle. Contents of the invention [0003] In order to overcome the deficiencies in the prior art, the object of the present invention is to provide a peak-valley timer that increases power consumption during off-peak hours at night, makes the grid power consumption more balanced, and reduces the user's power consumption cost. [0004] In order to solve the above-mentioned technical problems and achieve the above-mentioned purpose, the present invention adopts the following technical scheme: a peak-valley power consumption timer, including a programmable control chip U1, which also includes NAND gates U2, U3 and U4, the NA...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K17/296
Inventor 张晓鹤
Owner 苏州高新区禾云设备设计事务所
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