AFDX network switch with space-time separation

Abstract

The invention discloses an AFDX (avionics full-duplex switch Ethernet) network switch with a time-space separation characteristic. The AFDX network switch comprises N input ports, N output ports, 2N DMAs (direct memory accesses), a switch controller and N memories, wherein each input port is connected with one memory by one DMA, and the memory is further connected with an output port by one DMA; and the 2N DMAs are connected with the switch controller. The switch with a time-space separation characteristic in an AFDX system provided by the invention is easy to realize by software and hardware; and in case of keeping 100% of throughput, the time delay of a data package after passing through the switch, the queuing time delay of the data package in a buffer area of the switch, and the queue size of the buffer area are respectively and greatly reduced.

Description

technical field [0001] The invention relates to a switch, in particular to an aviation full-duplex switched Ethernet (AvionicsFullDupleXethernet, AFDX) network switch with the characteristic of time-space separation. Background technique [0002] As a new type of aviation data bus, AFDX aims to provide a safe and reliable transmission solution for high-performance avionics systems and meet flight control requirements under complex and harsh conditions. As early as the end of the last century, the giants of the world's aviation industry, Boeing and Airbus, shifted their research focus to using commercial Ethernet technology to transform the next-generation flight control bus. The research results led to the creation of AFDX. Airbus has successfully applied it to the A380 project, and Boeing has made clear plans to use the technology on Boeing787. Based on IEEE802.3, the AFDX network solution is adapted to the special requirements of the avionics subsystem, making it an avia...

AI Technical Summary

Problems solved by technology

However, the shared memory architecture also has obvious disadvantages, that is, its capacity and bandwidth are not easy to expand, and the delay and jitter of data packets passing through the switch are very large

The architecture of the shared memory switch in the prior art is as follows: figure 1 As shown, there are two bottlenecks in the shared memory architecture. The first is the shared memory. The capacity and bandwidth of the shared memory are the upper limit of the capacity and bandwidth of the entire switch. With the current memory technology, the capacity and bandwidth of the shared memory are far away. It is far from the requirements of the AFDX network; the second is the switch controller. Since there is only one switch controller, the burden on the switch controller is very heavy, and each time slot switch must take turns for all input ports and output ports. , which will inevitably cause the time when the data packet enters the switch and leaves the switch is uncertain, that is, the delay and jitter are very large

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