Implementation method and device of simd structure floating point division in gpdsp

Abstract

The invention discloses a method and device for achieving an SIMD structure floating point division in a general-purpose digital signal processor (GPDSP). The method comprises a first step of inputting two double precision floating point data or two groups of parallel SIMD double and single precision floating point data, adopting an SRT algorithm to perform division iterative computation and perform one-stage execution or multi-stage execution by truncation, executing repeated iterative computation in every stage, and enabling the times of iterative computation in every stage to be smaller than or equal to the maximum instruction cycle of the GPDSP; a second step of normalizing the mantissa of quotients according to data types and the number of stages executed in iterative computation, and obtaining a final quotient result after combination. The device comprises an iterative computation module corresponding to the method and a normalization processing module. The method and device for achieving the SIMD structure floating point division in the GPDSP can achieve double precision and SIMD double and single precision floating point division on identical hardware and have the advantages that the achieving method is simple, the application is flexible, hardware expenditure is small, the execution cycle is short, the delay is small, and division execution efficiency is high.

Description

technical field [0001] The invention relates to the technical field of division operation in GPDSP, in particular to a method and device for realizing floating-point division of SIMD structure in GPDSP. Background technique [0002] In scientific computing, voice communication, graphics acceleration, digital signal processing and other fields, a large number of single-precision floating-point division or double-precision floating-point division operations are required, so the performance of floating-point division will become the bottleneck of the overall performance of the processor. . In SPEC92, floating-point division instructions account for about 3% of the total number of instructions, but the calculation overhead of division accounts for 40% of the total time overhead. Therefore, designing a floating-point division with high execution efficiency is of great significance to the improvement of processor performance. . [0003] At present, the division hardware implemen...

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Problems solved by technology

Chinese patent application CN1979411A discloses a method and device for realizing a high-speed divider. In this scheme, the divider first uses a lookup table to find the reciprocal of the divisor, and then multiplies it with the dividend to obtain the quotient. Although the operation speed is relatively fast, it can greatly reduce the number of division operations. The clock cycle of the operation, but the operation accuracy is limited and the hardware overhead is relatively large

Chinese patent application CN1287037A discloses a high-radix divider and method. In this scheme, the divider obtains a k-bit quotient at a time, and can realize a divider with a base of 2, a base of 4 or even a higher base. Although the base in this scheme is small and the structure is simple, But the cycle required for the division operation is long

In GPDSP (General-Purpose Digital Signal Processor, general-purpose digital signal processor), the execution cycle of commonly used floating-point addition and subtraction, multiplication and other instructions generally does not exceed seven beats, while only the execution cycle of floating-point division instructions is tens of beats , such as base 16 double-precision floating-point division requires 14 iteration cycles, which increases the hardware complexity of the interrupt processing logic, making the high-base SRT divider not suitable for implementation in GPDSP

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