Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method

An imaging method and single-chip technology, applied in the field of signal processing, can solve the problems of slow DSP running speed, board error code, affecting the real-time performance and stability of imaging, and achieve the goal of ensuring accuracy, improving accuracy, and improving imaging real-time performance. Effect

Active Publication Date: 2014-12-17
BEIJING INSTITUTE OF TECHNOLOGYGY
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Problems solved by technology

However, the DSP runs slowly, and there are bit errors in the interaction b...

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  • Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method
  • Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method
  • Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method

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Embodiment Construction

[0041] The present invention will be described in detail below in conjunction with the accompanying drawings and specific examples.

[0042] A kind of Chirp Scaling imaging method based on single-chip FPGA of the present invention, as figure 1 As shown, the specific steps are:

[0043] Step 1: Construct the FFT calculation module, Doppler center frequency estimation and fitting module, Doppler FM slope estimation and fitting module, parameter calculation module, Chirp Scaling factor generation module, and range compensation factor generation on a FPGA module, azimuth compensation factor generation module, multiplication module, data transposition module, core calculation module and image quantization module, such as figure 2 shown.

[0044] Step 2: Perform data processing and Chirp Scaling factor generation in parallel:

[0045] The data processing is as follows: the FFT operation module reads the azimuth echo data from the echo data, and then performs the azimuth fixed-po...

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Abstract

The invention provides a monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method. The method specifically includes creating an FFT (fast Fourier transform) operation module, a Doppler center frequency estimating and fitting module, a Doppler frequency modulation slope estimating and fitting module, a parameter calculating module, a Chirp Scaling factor generating module, a range direction compensation factor generating module, an azimuth direction compensation factor generating module, a complex multiplication module, a data transposition module, a core calculation module and an image quantization module on an FPGA, and performing Chirp Scaling imaging according to the created modules. According to the method, the framework for realizing the Chirp Scaling imaging is analyzed, the degree of parallelism of imaging calculation is increased to the uttermost, the advantages of the FPGA can be given full play, and real-time performance of imaging is further improved.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and in particular relates to a Chirp Scaling imaging method based on a single chip FPGA. Background technique [0002] With the development of SAR imaging technology, the requirements for the resolution of spaceborne SAR are getting higher and higher, and the data rate of the original data increases sharply. Since the correlation of image data is much higher than that of the original echo data, if real-time imaging can be performed on the star, the image compression algorithm can greatly reduce the amount of data that needs to be transmitted. [0003] At present, the commonly used SAR imaging platforms include DSP, FPGA+DSP, FPGA+ASIC+DSP, among which FPGA has strong parallel processing capability and is suitable for processing large batches of data that are not too complicated, while DSP has strong flexibility and is suitable for processing more complex ones. Computing, ASIC is highly...

Claims

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Application Information

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IPC IPC(8): G01S13/90
CPCG01S7/02G01S13/90G01S13/9011
Inventor 陈禾闫雯曾涛龙腾
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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