Device and method for carrying out complex multiplication and butterfly calculation by virtue of floating point unit of processor

A floating-point multiplication and floating-point unit technology, which is applied in complex mathematical operations, machine execution devices, and concurrent instruction execution, can solve problems such as inability to meet real-time requirements, low utilization of hardware resources, large volume and power consumption, etc. Achieve good real-time performance and resource utilization, realize parallel and pipeline computing, and save hardware resources

Active Publication Date: 2015-01-28
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Summary
  • Abstract
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  • Application Information

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Problems solved by technology

The application-specific integrated circuit combination method has the disadvantages of complex circuit, large volume and power consumption, poor flexibility, etc., and the circuit function is fixed and cannot be configured. The calculation speed is slow and cannot meet the real-time requirements of modern digital signal processing

Method used

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  • Device and method for carrying out complex multiplication and butterfly calculation by virtue of floating point unit of processor
  • Device and method for carrying out complex multiplication and butterfly calculation by virtue of floating point unit of processor
  • Device and method for carrying out complex multiplication and butterfly calculation by virtue of floating point unit of processor

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Embodiment Construction

[0022] The present invention will be further described below in conjunction with the accompanying drawings and embodiments, and the present invention includes but not limited to the following embodiments.

[0023] Adopted following circuit design scheme among the present invention:

[0024] Firstly, in the present invention, the floating point unit is designed as a floating point addition unit FaCell and a floating point multiplication unit FmCell.

[0025] The input signal of the floating-point addition unit FaCell includes an enable signal FaEn, an operation mode Mode, a data input DataA, and a data input DataB. When the enable signal FaEn is effective, the floating-point addition unit performs a floating-point addition and subtraction operation, otherwise Do not perform any operation, and the operation mode Mode selects floating-point addition and floating-point subtraction operations. The output signal of the floating-point addition unit FaCell includes an enable signal o...

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Abstract

The invention provides a device and a method for carrying out complex multiplication and butterfly calculation by virtue of a floating point unit of a processor. The floating point unit is divided into a floating point addition unit and a floating point multiplication unit, wherein a few interconnection lines are additionally arranged between data ports of the floating point addition unit and the floating point multiplication unit; a special data path is formed between the floating point addition unit and the floating point multiplication unit; real and imaginary components of a complex are input into a data port of the floating point unit according to a determined ordering rule; the floating point complex multiplication and floating point complex butterfly calculation can be achieved under the control of decoding signals generated by a decoding unit. According to the method and the device, hardware resources are saved; compared with the existing complex multiplication and butterfly calculation function unit, the flexibility is further improved; meanwhile, parallel and flow calculation of a large amount of data can be well implemented; high real-time performance and high resource utilization rate are obtained.

Description

technical field [0001] The invention belongs to the technical field of digital circuits, and is suitable for fast calculation of signal processing algorithms such as FFT related to floating-point complex multiplication and butterfly operation in digital signal processing. Background technique [0002] In digital signal processing, a large number of floating-point complex multiplication and butterfly operations are involved. Due to the large amount of data and the complex processing process in signal processing, digital signal processors cannot well meet the real-time requirements of data processing. With the rapid development of large-scale integrated circuit technology, more and more signal processing algorithms are directly implemented in the form of hardware, which provides a new way to improve the real-time performance of data processing, not only reduces the delay of system processing data, Moreover, the reliability of the system is enhanced, and the working efficiency...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14G06F9/38
Inventor 冯春阳闫鑫杨靓高向强周泉
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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