Method for verifying validity of post-simulation extraction file

Abstract

The invention provides a method for verifying the validity of a post-simulation extraction file. The method includes the steps of a, drawing a first verification layout for a to-be-verified model, and adjusting parameters of the model to enable obtained characteristic parameters and testing parameters to be same; b, additionally arranging a validity verification module on the first verification layout, and obtaining a second verification layout; c, respectively simulating the first verification layout and the second verification layout, and extracting characteristic parameters; d, comparing the characteristic parameters of the second verification layout with the characteristic parameters of the first verification layout, and if the difference value between the characteristic parameters of the second verification layout and the characteristic parameters of the first verification layout is within an error margin range, considering that the post-simulation file is correct. According to the method, the validity verification module is additionally arranged on the basis of the original verification layout, influences of parasitic parameters introduced during layout wiring on the simulation result are converted into changes of the characteristic parameters of the verification layout, the validity of the post-simulation extraction file can be conveniently judged according to the changes of the characteristic parameters accordingly, and the defects of the prior art are effectively overcome.

Description

technical field [0001] The invention relates to the field of reference modeling of IC devices, in particular to a method for correctness of simulation extracted files after verification. Background technique [0002] With the development of integrated circuit technology and its more and more widely used, the requirements of high reliability, high performance and low cost must be considered in the design of integrated circuits. The function and accuracy requirements of analysis and reliability prediction are also getting higher and higher. In ICCAD software, the device model of MOSFET is the key link linking IC design and IC product function and performance. With the size of integrated devices getting smaller and smaller, the scale of integration is getting bigger and bigger, and the process of integrated circuits is getting more and more complex, and the requirements for the accuracy of device models are getting higher and higher. Today, an accurate MOSFET model has undoub...

AI Technical Summary

Problems solved by technology

[0003] MOSFET models generally require a verification circuit for verification. However, the influence of parasitic parameters brought about by layout and wiring will inevitably be introduced during circuit verification. If the simulation results are different from the test results, it is difficult to distinguish whether the accuracy of the model is insufficient or the accuracy of simulation extraction after layout not enough

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