Clock comprehensive result evaluation method based on time sequencing dependency relation

Abstract

The invention discloses a clock comprehensive result evaluation method based on a time sequencing dependency relation. The method comprises the steps of conducting clustering on a clock synchronization unit based on a time sequencing dependency relation; conducting an evaluation of a clock comprehensive result on a single cluster. According to the clock comprehensive result evaluation method based on the time sequencing dependency relation, the evaluation method can be applied in rich and traditional clock comprehensive evaluation, the data path omitted in the clock comprehensive (CTS) process is integrated into final clock comprehensive evaluation in the form of clustering, a user of a clock comprehensive tool can have clearer and more accurate cognition of the result of the clock comprehensive (CTS) by combining time sequencing constraints to some degree, thus the most effective constraint configuration can be executed, the meaningless process iteration is avoided, and thus the purpose that the design process is accelerated and the design efficiency is improved is achieved.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to a method for evaluating clock synthesis results of circuit design. Background technique [0002] Ultra-deep submicron and nano-technology are becoming more and more mature under the urging of applications such as the Internet, mobile phones, and the Internet of Things. Integrated circuit design, which is between market application and manufacturing industry, is confronted with great challenges. [0003] Clock synthesis belongs to the back-end design in circuit design. Specifically, after physical layout and before wiring, it mainly completes the effective clock path connection from the clock source point to all synchronous units on the clock. For the back-end design, it is a necessary condition for the completion of the circuit to meet the timing constraints, and the quality of the clock synthesis affects the results of the timing analysis. [0004] At present, the mains...

AI Technical Summary

Problems solved by technology

Statistics based on the clock tree is a rather coarse-grained analysis that does not reflect the clock tree synthesis between synchronization units with timing dependencies, which often leads to higher and stricter requirements for clock synthesis and increases the design process. The number of iterations in , reducing the design efficiency

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