PECI bus verification method and system supporting multiple slaves

A bus verification, bus technology, applied in the direction of functional inspection, response to error generation, detection of faulty computer hardware, etc., to achieve the effect of reliable design principle, wide application prospect and simple structure

Active Publication Date: 2017-08-01
GUANGDONG INSPUR BIG DATA RES CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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There is no method for verif...

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  • PECI bus verification method and system supporting multiple slaves
  • PECI bus verification method and system supporting multiple slaves

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Embodiment Construction

[0067] In order to make the purpose, features and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in the specific embodiments of the present invention.

[0068] Embodiment 1 of the present invention provides a PECI bus verification method supporting multiple slaves, comprising the following steps:

[0069] Step 1. Define the model; define the host model, define the slave model, and define the top layer of the test environment; the host model includes read and write process units;

[0070] Specific steps are as follows:

[0071] Define the host model; the host model includes input ports, output ports, read and write process units;

[0072] Define the slave model; the slave model includes input and output ports and several state machines;

[0073] Define the top level of the test environment;

[0074] The top layer of the test e...

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Abstract

The invention provides a PECI bus verification method and system supporting multiple slaves. The method comprises the steps that 1, models are defined, wherein a host model, a slave model and a test environment top are defined, and the host model comprises a read-write process unit; 2, the test environment top generates test excitation, and the test excitation is input into an input port of the host model; 3, the host model creates a read-write process task to a to-be-tested PECI bus interface according to the test excitation through the read-write process unit; 4, the to-be-tested PECI bus interface sends the read-write process task to the slave model through a PECI bus; 5, the slave model responds to the read-write process task and sends returned data, and the returned data arrives at the host model through the to-be-tested PECI bus interface; 6, the host model outputs the returned data to the test environment top from an output port; and 7, the test environment top judges the correctness of the returned data according to the test excitation, and whether the to-be-tested PECI bus interface has an error is judged.

Description

technical field [0001] The invention belongs to the field of hardware testing, and in particular relates to a PECI bus verification method and system supporting multiple slaves. Background technique [0002] PECI is a new-generation digital interface proposed by Intel, which is a dedicated single-wire bus between the processor and the system stability monitoring device. It is used between BMC and processor in the server field to read CPU temperature and read and write related device information. The transmission of the PECI bus is based on specific commands of the protocol. The format of the command is divided into address, write length, read length, write data, FCS, and read data. There is no method for verifying the PECI bus in the prior art. [0003] This is the deficiency of the prior art. Therefore, aiming at the above-mentioned defects in the prior art, it is very necessary to provide a PECI bus verification method and system supporting multiple slaves. Contents of...

Claims

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Application Information

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IPC IPC(8): G06F11/10G06F11/26
CPCG06F11/1004G06F11/26
Inventor 王硕唐涛石广谢凯元
Owner GUANGDONG INSPUR BIG DATA RES CO LTD
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