Cyclic redundancy check CRC implementation method, apparatus and network device

Abstract

The present application provides a CRC implementation method, apparatus and network device that can reduce the CRC computation complexity of data to be verified, thereby improving CRC computation performance. An embodiment method of the present invention comprises that: the CRC effecting means divides the data to be checked into K segments of subdata in an order from low to high bits, the number of bits of data to be verified is equal to the data bit width of the CRC effecting means, K is an even number greater than or equal to 2;CRC computation for each of the K segments of sub-data, resulting in K CRC results; the K CRC results are inverse corrected in order from high to low, resulting in a final CRC result.

Description

technical field [0001] The present application relates to the field of communication technologies, and in particular to a method, device and network equipment for implementing a cyclic redundancy check (Cyclic Redundancy Check, CRC). Background technique [0002] In the process of field-programmable gate array (Field-Programmable Gate Array, FPGA) logic implementing interface communication, in order to improve the reliability of data transmission, a method of adding check digits to data is generally used for transmission. The most commonly used in the current data verification algorithm is the CRC algorithm. [0003] With the development of communication technology and the increase in the demand for user communication data, the communication interface rate is required to be faster and faster. When the CRC device calculates the CRC, the CRC calculation module needs to process the bits of the data to be verified within one shot sequence. The larger the number, the larger the ...

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Problems solved by technology

[0004] but, figure 1 In the shown CRC implementation method, when the data bit width (for example, the bit width is 1024 bits) becomes larger, a large number of calculation modules need to be added for CRC calculation, and combinational logic is used to realize the logic of selecting 1 from 128. The increased computational complexity leads to The increase in the number of Look Up Table (LUT) series inside the FPGA logic affects the timing of CRC calculations, resulting in a significant drop in CRC calculation performance; and figure 2 Although the CRC implementation method shown reduces the resource consumption of the calculation module, the increase in the number of processing stages of the FPGA logic will also affect the timing of the CRC calculation, which will affect the performance of the CRC calculation.

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