Adaptive routing algorithm for heterogeneous network-on-chip

A heterogeneous on-chip, self-adaptive technology, used in data exchange networks, digital transmission systems, electrical components, etc.

Inactive Publication Date: 2019-04-05
魏莹
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

The newly added non-cache router in the algorithm is based on the deflection routing method, and there is still a lot of room for improvement

Method used

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  • Adaptive routing algorithm for heterogeneous network-on-chip

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Embodiment Construction

[0012] figure 1 The schematic diagram of the optimization strategy for the selection of the output port is shown, and the data flake selects a sub-optimal output port to perform the second competition arbitration, so that the probability of misinformation of the data flake is reduced. When the data flake arrives at the routing node, the effective output port and the suboptimal output port of the data flake must be calculated first. Assume that the current routing node coordinates are (Xc, Yc), and the destination node coordinates are (Xd, Yd). Set a flit_info structure for each data flit, including timestamp, effective output port first and suboptimal output port second. When Xd>Xc, if Yd>Yc), then set the first of the data slice to be down, and second to be right; if YdYc), then set first to be down, and second to be left; if YdYc), then set first to be down, and second to be -1; if Yd

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Abstract

In view of the diversity of running applications of the network-on-chip, a heterogeneous network as a relatively flexible network structure can reduce the transmission delay of the network and improvethe system performance. An adaptive routing algorithm for a heterogeneous network-on-chip is invented, and a static routing algorithm and a dynamic adaptive routing algorithm are used in a matching manner to transmit data packets. Meanwhile, an optimization algorithm for the adaptive routing algorithm is also invented. According to the algorithm, improvement is made on the bufferless routing partadded to the adaptive routing algorithm, and second competition arbitration of a data microchip is used to reduce the misinformation probability of data microchip deflection. Therefore, the transmission delay of a data microchip in the network is reduced, and the network performance is improved.

Description

Technical field [0001] The invention relates to the design of on-chip network, in particular to the design of non-buffer routing algorithm of heterogeneous on-chip network. Background technique [0002] Network on chip is a new communication method of system on chip. It is the main component of multi-core technology. The network-on-chip approach brings a new method of on-chip communication that significantly outperforms the performance of traditional bus-based systems (bus). The network-on-chip system can better adapt to the global asynchronous and local synchronous clock mechanism used in the design of complex multi-core system-on-chip in the future, and is an inevitable choice for the new generation of complex computing architecture. Aiming at the diversity of applications running on the network on chip, the heterogeneous network is a relatively flexible network structure, which uses a variety of cores with different functions. A heterogeneous multi-core system-on-a-chi...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/721H04L12/803H04L12/937
CPCH04L45/12H04L47/125H04L49/254
Inventor 魏莹
Owner 魏莹
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