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Prefetch FIFO circuit and prefetch FIFO method

A prefetching and circuit technology, applied in electrical digital data processing, special data processing applications, data transformation, etc., can solve the problem of large data transmission delay, and achieve the effect of reducing delay and reducing the effect of delay

Active Publication Date: 2019-11-12
NANJING SEMIDRIVE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prefetch FIFO design using custom physical memory, due to the circuit characteristics of the memory itself, it takes a long time for the data to enter the prefetch FIFO unit and be read out, which leads to the delay of data transmission in the prefetch FIFO larger

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  • Prefetch FIFO circuit and prefetch FIFO method
  • Prefetch FIFO circuit and prefetch FIFO method
  • Prefetch FIFO circuit and prefetch FIFO method

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Embodiment Construction

[0041] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0042] figure 1 It is a block diagram of a prefetch FIFO circuit according to the present invention, as figure 1 As shown, the prefetching FIFO circuit provided by the present invention includes FIFO controller (FIFO_Controller) 101, RAM memory 102, buffer register group (buffer_regs) 103, buffer controller (buffer_Controller) 104, output register group (output_regs) 105, output Controller (output_Controller) 106, state machine (STATE_MACHINE) 107, first data selection module 108, second data selection module 109, first matrix module 110 and second matrix module 111;

[0043] Wherein, FIFO controller 101, it is respectively connected with RAM memory 102, cache cont...

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Abstract

The invention provides a prefetching FIFO circuit. The prefetching FIFO circuit comprises an FIFO controller, an RAM memory, a cache register set, a cache controller, an output register set, an outputcontroller, a state machine, a first data selection module, a second data selection module, a first matrix module and a second matrix module. The invention further provides a data first-in first-outmethod, whether the data is skipped over the RAM or not can be selectively determined through control of the state machine and is directly stored in the output register set, and the delay of data transmission is greatly saved.

Description

technical field [0001] The invention belongs to the field of electronic circuit design, in particular to a prefetch FIFO circuit. Background technique [0002] In the design of logic circuits, FIFO (First_In_First_Out) is one of the most commonly used circuit units. According to the difference of data delay, FIFO can be divided into prefetch FIFO and non-prefetch FIFO, and many complex logic designs need to use prefetch FIFO to meet the requirements of application functions. [0003] A common prefetch FIFO includes a memory storage unit, a FIFO control circuit, and a data prefetch control circuit. After the data enters the prefetch FIFO, it will first be cached in the memory storage unit, and then the FIFO controller and the data prefetch circuit complete the reading of the data. fetch function. The Memory storage unit is mainly divided into register groups and physical IP units. In ASIC circuit design, register groups are usually used to build storage units only in applic...

Claims

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Application Information

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IPC IPC(8): G06F5/06G06F5/08G06F9/30G06F17/50
CPCG06F5/06G06F5/08G06F9/30098
Inventor 高稳元
Owner NANJING SEMIDRIVE TECH CO LTD